System Timer
UG0331 User Guide Revision 15.0 616
19.2.2.3 Interrupts
There are two interrupt signals from the system timer block—TIMER1INT and TIMER2INT. The
TIMER1INT signal is mapped to INTISR[14] and the TIMER2INT signal is mapped to INTISR[15] in the
Cortex-M3 processor nested vectored interrupt controller (NVIC) controller. Both interrupt enable bits
within the NVIC (INTISR[14] and INTISR[15]) correspond to bit locations 14 and 15. These interrupts are
enabled by setting the appropriate TIMxINTEN bits in TIM1_CTRL, TIM2_CTRL, or TIM64_CTRL
registers.
In 32-bit mode, the TIMxRIS bit in the respective interrupt service routine must be cleared to prevent a
reassertion of the interrupt. Similarly, in 64-bit mode, TIM64RIS bit in the respective interrupt service
routine must be cleared to prevent a reassertion of the interrupt.
19.2.3 Details of Operation
19.2.3.1 Timer Operating Modes
The Timers can be configured to operate in the following modes:
• Periodic Mode
• One-Shot Mode
• 64-Bit and 32-Bit Modes
The following sections explain the modes of operation.
19.2.3.1.1 Periodic Mode
In this mode, the counter generates the interrupts at constant intervals. On reaching zero, the counter is
reloaded with a value held in a register and counting restarts.
Periodic mode is selected by setting the TIMxMODE bit in the TIMx_CTRL register to 0. In this mode, the
counter continually counts down to zero when it is enabled. On reaching zero, an interrupt is generated
and the counter is reloaded with the value stored in the TIMx_LOADVAL register. The counter then
continues to count down towards zero, without waiting for the interrupt to be cleared. The interrupt
remains asserted until cleared by the processor. If the counter reaches zero without clearing the previous
interrupt, the counter behaves as if it has just timed out (reached zero). In effect, an interrupt is lost. It can
continue indefinitely as long as the counter is enabled in Periodic mode and interrupts are not cleared.
Writing to the TIMxLOADVAL register at any time causes the counter to be loaded immediately with the
value written, and, if enabled, it will continue counting down from the new value. If the
TIMx_BGLOADVAL (background load value) register is written, the value written overwrites the
TIMxLOADVAL register. The counter is not updated immediately with the new value. However, when the
counter reaches zero, it is loaded with the new value contained in the TIMxLOADVAL register. By making
use of the TIMxBGLOADVAL register, it is possible to continually generate interrupts with varying or
alternating time intervals between interrupts without having any arbitrary variation in the lengths of the
intervals due to (possibly) different cycle counts for servicing successive interrupts. For example, this
approach is used to allow a processor to generate a waveform with a non-equal mark-space ratio on a
general purpose output pin.
19.2.3.1.2 One-Shot Mode
The counter generates a single interrupt in this mode. On reaching zero, the counter halts until
reprogrammed.
One-shot mode is selected by setting the TIMxMODE bit in the TIMx_CTRL register to 1. In this mode,
the counter stops on reaching zero and a single interrupt is generated. When the counter is stopped in
One-shot mode, it can be restarted by writing a non-zero value to the TIMx_LOADVAL register.
Alternatively, the counter can be restarted by clearing the TIMxMODE bit. This causes the counter to be
loaded with the value held in the TIMx_LOADVAL register and to begin operating in Periodic mode.
While the counter is counting down, it is possible to change the value of the TIMxMODE bit at any time
without affecting the operation. For example, if the counter is decrementing in One-shot mode and the
TIMxMODE bit is cleared before the counter reaches zero, the counter begins to operate in Periodic
mode on reaching zero.
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