Microsemi SmartFusion2 - Table 163 HPDMAD0 SR_REG; Table 164 HPDMAD1 SR_REG

High Performance DMA Controller
UG0331 User Guide Revision 15.0 257
8.4.1.14 Descriptor 0 Status Register
8.4.1.15 Descriptor 1 Status Register
Table 163 • HPDMAD0SR_REG
Bit
Number Name
Reset
Value Description
0 HPDMASR_DCP_ACTIVE[0] 0 Descriptor 0 transfer in progress.
1: Descriptor 0 transfer in progress.
0: Descriptor 0 is in queue when HPDMACR_DCP_VALID[0]
bit is set in descriptor 0 Control register.
1 HPDMASR_DCP_CMPLET[0] 0 Descriptor 0 transfer complete.
1: Descriptor 0 transfer completed successfully
0: Descriptor 0 transfer not completed
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0]
of the descriptor 0 control register.
2 HPDMASR_DCP_SERR[0] 0 Descriptor 0 source transfer error.
1: Descriptor 0 transfer error occurred at source end.
0: No error at source end during descriptor 0 transfer
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0
]
of the descriptor 0 Interrupt Clear register.
3 HPDMASR_DCP_DERR[0] 0 Descriptor 0 destination transfer error.
1: Descriptor 0 transfer error
0: No error at destination end during descriptor 0 transfer.
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[0]
of the descriptor 0 Interrupt Clear register.
31:4 Reserved 0 Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Table 164 • HPDMAD1SR_REG
Bit
Number Name
Reset
Value Description
0 HPDMASR_DCP_ACTIVE[1] 0 Descriptor 1 transfer in progress.
1: Descriptor 1 transfer in progress.
0: Descriptor 1 is in queue when HPDMACR_DCP_VALID[1]
bit is set in Descriptor 1 Control register.
1 HPDMASR_DCP_CMPLET[1] 0 Descriptor 1 transfer complete.
1: Descriptor 1 transfer completed successfully
0: Descriptor 1 transfer not completed
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1]
of the descriptor 1 Control register.
2 HPDMASR_DCP_SERR[1] 0 Descriptor 1 source transfer error.
1: Descriptor 1 transfer error occurred at source end
0: No error at source end during descriptor 1 transfer
This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1]
of the descriptor 1 Interrupt Clear register.