Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 77
3.6.6.1.3 Restrictions
In these instructions, do not use SP and do not use PC.
If you use the
S
suffix with the
MUL
instruction:
•
Rd
,
Rn
, and
Rm
must all be in the range
R0
to
R7
•
Rd
must be the same as
Rm
• you must not use the
cond
suffix.
3.6.6.1.4 Condition Flags
If
S
is specified, the
MUL
instruction:
• updates the N and Z flags according to the result
• does not affect the C and V flags.
Examples
MUL R10, R2, R5 ; Multiply, R10 = R2 x R5
MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2
MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2
MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6).
3.6.6.2 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a
64-bit result.
3.6.6.2.1 Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
• op is one of:
•
UMULL
: Unsigned Long Multiply
•
UMLAL
: Unsigned Long Multiply, with Accumulate
•
SMULL
: Signed Long Multiply
•
SMLAL
: Signed Long Multiply, with Accumulate
• cond is an optional condition code, see Conditional Execution, page 55.
• RdHi, RdLo are the destination registers. For
UMLAL
and
SMLAL
they also hold the accumulating
value.
• Rn, Rm are registers holding the operands.
3.6.6.2.2 Operation
The
UMULL
instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies these
integers and places the least significant 32 bits of the result in
RdLo
, and the most significant 32 bits of the
result in
RdHi
.
The
UMLAL
instruction interprets the values from
Rn
and
Rm
as unsigned integers. It multiplies these
integers, adds the 64-bit result to the 64-bit unsigned integer contained in
RdHi
and
RdLo
, and writes the
result back to
RdHi
and
RdLo
.
The
SMULL
instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers. It
multiplies these integers and places the least significant 32 bits of the result in
RdLo
, and the most
significant 32 bits of the result in
RdHi
.
The
SMLAL
instruction interprets the values from
Rn
and
Rm
as two’s complement signed integers. It
multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in
RdHi
and
RdLo
,
and writes the result back to
RdHi
and
RdLo
.
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