Microsemi SmartFusion2 - Table 214 CSR0 L_REG (Host)

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 318
10.3.6.3 CSROL_REG (Host mode) Bit Definitions
5 SendStall 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to terminate
the current transaction. The STALL handshake will be transmitted and then
this bit will be cleared automatically.
4 SetupEnd 0 This bit is set when a control transaction ends before the DataEnd bit (bit[3] of
this register) has been set. An interrupt is generated and the FIFO is flushed
at this time. The bit is cleared by the Cortex-M3 processor (or fabric master)
writing a 1 to the ServicedSetupEnd bit (bit[7] of this register).
3 DataEnd 0 The Cortex-M3 processor (or fabric master) sets this bit:
– When setting TxPktRdy (bit[1] of this register) for the last data packet.
– When clearing RxPktRdy (bit[0] of this register) after unloading the last data
packet.
– When setting TxPktRdy (bit[1] of this register) for a zero length data packet.
It is cleared automatically.
2 SentStall 0 This bit is set when a STALL handshake is transmitted. The Cortex-M3
processor (or fabric master) should clear this bit.
1 TxPktRdy 0 The Cortex-M3 processor (or fabric master) sets this bit after loading a data
packet into the FIFO. It is cleared automatically when a data packet has been
transmitted. An interrupt is also generated at this point (if enabled).
0 RxPktRdy 0 This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The Cortex-M3 processor (or fabric master)
clears this bit by setting the ServicedRxPktRdy bit (bit[6]of this register).
Table 214 • CSR0L_REG (Host)
Bit
Number Name
Reset
Value Function
7 NAK Timeout 0 This bit is set when endpoint 0 is halted, following the receipt of NAK responses
for longer than the time set by the NAKLimit0 register. The Cortex-M3 processor
(or fabric master) should clear this bit to allow the endpoint to continue.
6 StatusPkt 0 The Cortex-M3 processor (or fabric master) sets this bit at the same time as the
TxPktRdy (bit[1] of this register) or ReqPkt bit (bit 0 of this register) is set, to
perform a status stage transaction. Setting this bit ensures that the data toggle is
set to 1 so that a DATA1 packet is used for the status stage transaction.
5 ReqPkt 0 The Cortex-M3 processor (or fabric master) sets this bit to request an IN
transaction. It is cleared when RxPktRdy (bit [0] of this register) is set.
4 Error 0 This bit will be set when three attempts have been made to perform a transaction
with no response from the peripheral. The Cortex-M3 processor (or fabric master)
should clear this bit. An interrupt is generated when this bit is set.
3 SetupPkt 0 The Cortex-M3 processor (or fabric master) sets this
bit, at the same time as the
TxPktRdy bit (bit[1] of this register) is set, to send a SETUP token instead of an
OUT token for the transaction.
Setting this bit also clears the Data Toggle.
2 RxStall 0 This bit is set when a STALL handshake is received. The Cortex-M3 processor (or
fabric master) should clear this bit.
Table 213 • CSR0L_REG (Peripheral) (continued)
Bit
Number Name
Reset
Value Function