Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 88
3.6.10 Miscellaneous Instructions
The following table lists the remaining Cortex-M3 processor instructions:
3.6.10.1 BKPT
Breakpoint.
3.6.10.1.1 Syntax
BKPT #imm
where:
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
3.6.10.1.2 Operation
The
BKPT
instruction causes the processor to enter Debug state. Debug tools can use this to investigate
system state when the instruction at a particular address is reached.
imm
is ignored by the processor. If required, a debugger can use it to store additional information about
the breakpoint.
The
BKPT
instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the
condition specified by the
IT
instruction.
3.6.10.1.3 Condition Flags
This instruction does not change the flags.
Examples
BKPT #0x3 ; Breakpoint with immediate value set to 0x3 (debugger can
; extract the immediate value by locating it using the PC)
Note: ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any
purpose other than Semi-hosting.
3.6.10.2 CPS
Change Processor State.
Table 38 • Miscellaneous Instructions
Mnemonic Brief Description See
BKPT Breakpoint BKPT, page 89
CPSID Change Processor State, Disable Interrupts CPS, page 89
CPSIE Change Processor State, Enable Interrupts CPS, page 89
DMB Data Memory Barrier DMB, page 90
DSB Data Synchronization Barrier DSB, page 91
ISB Instruction Synchronization Barrier ISB, page 91
MRS Move from special register to register MRS, page 91
MSR Move from register to special register MSR, page 92
NOP No Operation NOP, page 92
SEV Send Event SEV, page 93
SVC Supervisor Call SVC, page 93
WFE Wait For Event WFE, page 93
WFI Wait For Interrupt WFI, page 94
To Next Page
Loading...
