Microsemi SmartFusion2 - Page 124

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 90
3.6.10.4 DSB
Data Synchronization Barrier.
3.6.10.4.1 Syntax
DSB{cond}
where:
cond is an optional condition code, see Conditional Execution, page 55.
3.6.10.4.2 Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB , in
program order, do not execute until the DSB instruction completes. The DSB instruction completes when
all explicit memory accesses before it complete.
3.6.10.4.3 Condition Flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
3.6.10.5 ISB
Instruction Synchronization Barrier.
3.6.10.5.1 Syntax
ISB{cond}
where:
cond is an optional condition code, see Conditional Execution, page 55.
3.6.10.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all
instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been
completed.
3.6.10.5.3 Condition Flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
3.6.10.6 MRS
Move the contents of a special register to a general-purpose register.
3.6.10.6.1 Syntax
MRS{cond} Rd, spec_reg
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rd is the destination register.
spec_reg can be any of:
APSR , IPSR , EPSR , IEPSR , IAPSR , EAPSR , PSR , MSP , PSP , PRIMASK , BASEPRI ,
BASEPRI_MAX , FAULTMASK , or CONTROL .
Note: All the
EPSR and IPSR fields are zero when read by the MRS instruction.