Microsemi SmartFusion2 - Table 11 IPSR Bit Assignments; Table 10 Application Program Status Register

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 23
Access these registers individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example:
• Read all of the registers using PSR with the MRS instruction.
• Write to the APSR using APSR with the MSR instruction.
The following table shows the PSR combinations and attributes.
See the instruction descriptions in MRS, page 91 and MSR, page 92 for more information about how to
access the program status registers.
3.5.1.3.6 Application Program Status Register
The APSR contains the current state of the condition flags from previous instruction executions. See the
register summary in the following table for its attributes. The following table lists the bit assignments.
3.5.1.3.7 Interrupt Program Status Register
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the
register summary in Ta ble 8, page 21 for its attributes. The following table lists the bit assignments.
Table 9 • PSR Combinations and Attributes
Register Type Combination
PSR RW
1,2
1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes
to the these bits.
APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
IAPSR RW
1
APSR and IPSR
EAPSR RW
2
APSR and EPSR
Table 10 • Application Program Status Register
Bits Name Function
[31] N Negative flag
[30] Z Zero flag
[29] C Carry or borrow flag
[28] V Overflow flag
[27] Q Saturation flag
[27:0] - Reserved
Table 11 • IPSR Bit Assignments
Bits Name Function
[31:9] Reserved