AHB Bus Matrix
UG0331 User Guide Revision 15.0 224
7.1.3.2 HBURST Support for eNVM
The AHB bus matrix only supports AHB bursts from the Cortex-M3 processor bus or from the cache to
the eNVM. To support burst reads from the eNVM, you should program SW_WEIGHT_IC to be the
maximum burst expected. SW_WEIGHT_IC = 32 allows a cache line to be filled from eNVM without
interruption.
7.1.3.3 AHB Bus Matrix to Fabric Interface Controller
The AHB bus matrix provides two 2-bit side band signals—driven out of the AHB bus matrix to the fabric
interrupt controller to indicate which master is asserting FIC_X (X indicates FIC 0 or 1 master). The
following figure shows the two FIC blocks connected to AHB bus matrix.
The FIC block provides two separate interfaces between the MSS and the FPGA fabric: the hard master
(HM) and fabric master (FM). These interfaces may be configured to operate as AHB32 or APB32.
Configure FIC_0 and FIC_1 interfaces in bypass mode to perform weighted round robin arbitration. For
more information, refer to the AC388: SmartFusion2 SoC FPGA - Dynamic Configuration of AHB Bus
Matrix Application Note.
FIC_0_MASTER_ID and FIC_1_MASTER_ID are two signals from FIC_0 and FIC_1 to FPGA fabric that
indicate the current master group accessing fabric slaves. These two signals are exposed when each
FIC block interface towards the fabric is configured with the Libero SoC MSS configurator.
Figure 111 • AHB Bus Matrix to Fabric Interface Controller
The following table provides the decoding of master access done by the AHB bus matrix to the fabric
slave.
Table 145 • Decoding of Master Access to the Fabric Slaves
FIC_X_MASTER_ID Accessing Master
00 IC-bus, D-bus, and S-bus master
01 FIC_0, FIC_1 master
10 HPDMA, Ethernet master, PDMA, USB
11 System controller
AHB-to-AHB
Bridge with
Address
Decoder
MM4 MS4 MM5 MM6
FIC_0 FIC_1
Ethernet
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