Fabric Interface Interrupt Controller
UG0331 User Guide Revision 15.0 739
23.2 Functional Description
This section provides the detailed description of the FIIC subsystem.
23.2.1 Architecture Overview
The following figure shows the interfacing of the FIIC with NVIC, MSS peripheral interrupts, and FPGA
fabric. The FIIC receives 43 level-sensitive active high interrupts from the MSS as inputs. These MSS
peripheral interrupts are combined, in a predetermined fashion, into 16 M2F interrupts (MSS_INT_M2F
[15:0]) routed to the fabric. There is also a pass-through M3_NMI non-maskable interrupt from the
watchdog timer and COMM_BLK interrupt, COMM_BLK_INT.
Figure 320 • Block Diagram for Fabric Interface Interrupt Controller
There are 16 circuits, as shown in the following figure. Each circuit corresponds to a row in the preceding
figure. The dedicated interrupts coming from the MSS peripherals are always connected to the 16 M2F
interrupt signals.
Figure 321 • Combinational Circuit for Mapping MSS Interrupts to a MSS_INT_M2F
Every peripheral interrupt in the MSS except I2C_SMBALERT0, I2C_SMBSUS0, I2C_SMBALERT1, and
I2C_SMBSUS1, has access to the FPGA fabric through the dedicated inputs of the FIIC.
AHB Bus Matrix
Cache
Controller
SD IC
ARM Cortex-M3
Processor
SD I
APB_0
IDC
D/S
Nested Vector Interrupt
Controller (NVIC)
Fabric Interface Interrupt
Controller ( FIIC)
MSS_INT_M2F[15:0]
COMM_BLK_INT
M3_NMI
FPGA Fabric
MSS_INT_F2M[15:0]
MSS_INT_F2M[15:0]
MSS Peripheral Interrupts
43 MSS Peripheral
Interrupts
MSS_INT_M2F
Dedicated
Select Group 1
Select Group 0
SELECT_MODE
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