Microsemi SmartFusion2 - Functional Description; Figure 95 Esram_0 and Esram_1 Connection to AHB Bus Matrix; Table 118 Esram Block Sizes and Address Ranges

Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 188
The following figure depicts the connectivity of eSRAM_0 and eSRAM_1 to the AHB bus matrix.
Figure 95 • eSRAM_0 and eSRAM_1 Connection to AHB Bus Matrix
6.2 Functional Description
The following table lists the sizes of the eSRAM blocks and their address range.
Table 118 • eSRAM Block Sizes and Address Ranges
eSRAM Block
Physical
RAM4096X40
Block
Size and Address Range
with SECDED ON Size and Address Range with SECDED OFF
eSRAM_0 RAM4096X40_0 16 KB from 0x20000000 to
0x20003FFF and ECC from
0x20010000 to 0x20010FFF
16 KB from 0x20000000 to 0x20003FFF and
4 KB from 0x20010000 to 0x20010FFF
RAM4096X40_1 16 KB from 0x20004000 to
0x20007FFF and ECC from
0x20011000 to 0x20011FFF
16 KB from 0x20004000 to 0x20007FFF and
4 KB from 0x20011000 to 0x20011FFF
eSRAM_1 RAM4096X40_2 16 KB from 0x20008000 to
0x2000BFFF and ECC from
0x20012000 to 0x20012FFF
16 KB from 0x20008000 to 0x2000BFFF and
4 KB from 0x20012000 to 0x20012FFF
RAM4096X40_3 16 KB from 0x2000C000 to
0x2000FFFF and ECC from
0x20013000 to 0x20013FFF
16 KB from 0x2000C000 to 0x2000FFFF and 4
KB from 0x20013000 to 0x20013FFF
AHB Bus Matrix
eSRAM_0
System
Controller
Cache
Controller
SD IC
ARM Cortex-M3
Processor
SDI
MSS DDR
Bridge
PDMA
MS6
MM3
AHB To AHB Bridge with Address Decoder
USB OTG
HPDMA
MDDR
APB_0
SYSREG
Triple Speed
Ethernet MAC
FIC_0
MM4 MS4
MS2 MS3 MS0
MS5
MS1
MM5 MM6
MM7
MM8
MM2 MM1 MM0 MM9
IDC
D/S
eNVM_0 eNVM_1 eSRAM_1
FIC_2 (Peripheral
Initialization)
APB_1
MMUART_0
SPI_0
I2C_0
PDMA
Configuration
WATCHDOG
FIIC
TIMERx2
MMUART_1
SPI_1
I2C_1
GPIO
CAN
RTC
COMM_BLK
FIC_1
MSS_FIC MS6_USB
MS5_MAC MS5_SR MS5_APB0 MS5_FIC2 MS5_APB1