Microsemi SmartFusion2 - Table 353 MII_CONFIG; Table 354 MII_COMMAND

Ethernet MAC
UG0331 User Guide Revision 15.0 406
5 SCAN AUTO
INCREMENT
0x0 Setting this bit causes MII Mgmt to continually read from a
set of PHYs of contiguous address space. The starting
address of the PHY is specified by the content of the PHY
address field, which is recorded in the MII Mgmt Address
register. Up to 31 PHY contiguous address space can be
addressed. The last PHY, which is to be queried in this read
sequence, is the one residing at address 0x31, after which
the read sequence returns to the PHY, specified by the PHY
address field.
4 PREAMBLE
SUPPRESSION
0x0 Setting this bit causes MII Mgmt to suppress preamble
generation and reduce the Mgmt cycle from 64 clocks to 32
clocks. This is in accordance with the IEEE 802.3/22.2.4.4.2.
Clearing this bit causes MII Mgmt to perform Mgmt read/write
cycles with the 64 clocks of preamble.
3 Reserved 0x0 Reserved
2:0 MGMT CLOCK
SELECT
0x0 This field determines the clock frequency of the management
data clock (MDC). MGMT Clock Select Encoding
programming fields are given below.
Mgmt Clock Select 2 1 0
Source Clock divided by 4 0 0 0
Source Clock divided by 4 0 0 1
Source Clock divided by 6 0 1 0
Source Clock divided by 8 0 1 1
Source Clock divided by 10 1 0 0
Source Clock divided by 14 1 0 1
Source Clock divided by 20 1 1 0
Source Clock divided by 28 1 1 1
Table 354 • MII_COMMAND
Bit Number Name Reset Value Description
31:2 Reserved 0x0 Reserved
1 SCAN CYCLE 0x0 This bit causes MII Mgmt to perform Read cycles
continuously. This is useful for monitoring Link Fail.
0 READ CYCLE 0x0 This bit causes MII Mgmt to perform a single Read cycle. The
Read data is returned in Register 0xC (MII Mgmt Read Data).
Table 353 • MII_CONFIG (continued)
Bit Number Name Reset Value Description