Microsemi SmartFusion2 - MSS DDR Fabric Alignment Clock Controller (FACC) Configuration Register 1

System Register Block
UG0331 User Guide Revision 15.0 705
Note: Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior
for M2S005/010 Devices, page 682.
22.3.38 MSS DDR Fabric Alignment Clock Controller (FACC)
Configuration Register 1
0 FACC_PLL_BYPASS 0 Powers down the MPLL core and bypasses it such that
PLLOUT tracks REFCLK.
Table 694 • MSSDDR_FACC1_CR
Bit Number Name
Reset
Value Description
[31:28] Reserved 0
27 FACC_FAB_REF_SEL 0 Selects the source of the reference clock to be supplied to the
MPLL. Allowed values are:
0: 50 MHz RC
1: Fabric clock (CLK_BASE)
26 CONTROLLER_PLL_INIT 0x1 Indicates whether the FACC is to be configured for PLL
initialization mode. The user can write to it when it detects that
the MPLL has lost lock and it wants to switch to a known good
clock source until the MPLL comes back into lock. This causes
the 50 MHz clock to be selected through to the MSS. It also
interrupts the System Controller, which then waits for the MPLL
to come into lock before clearing this bit and thereby selecting
the MPLL output as the MSS clock source again. The allowed
values of this bit are:
0: The corresponding FACC multiplexer select lines or clock
gate control line co mes from the normal run-time configuration
signals (from relevant MSS system register bits).
1: The corresponding FACC multiplexer select lines or clock
gate control line are overridden by hardwired PLL initialization
selection, as described below:
– Override the four no-glitch multiplexers related to the aligned
clocks, so that they select CLK_STANDBY as the source of
M3_CLK, APB_0_CLK, APB_0_CLK and
DDR_SMC_FIC_CLK.
– Override the selection of the FACC standby multiplexer, so
that it selects the RCOSC_25_50MHZ clock as the source of
CLK_STANDBY.
– Override the selection of the FACC reference multiplexer, so
that it selects CLK_BASE clock as the source of
MPLL_REF_CLK.
– Override the value of the PLL bypass configuration signal, so
that it forces the MPLL bypass path not to be used.
– Force MDDR_CLK to be gated off.
Table 693 • MSSDDR_PLL_STATUS_HIGH_CR (continued)
Bit Number Name
Reset
Value Description