High Performance DMA Controller
UG0331 User Guide Revision 15.0 261
8.4.1.21 Descriptor 3 Pending Transfers Register
8.4.1.22 HPDMA Interrupt Clear Register
Table 170 • HPDMAD3PTR_REG
Bit
Number Name
Reset
Value Description
15:0 HPDMAPTR_D3_SRC_PNDNG 0 Descriptor 3 source pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the source end of descriptor 3.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the source during descriptor 0 transfer.
31:16 HPDMAPTR_D3_DST_PNDNG 0 Descriptor 3 destination pending transfers in words.
This register indicates the internal transfer size counter
corresponding to the destination end of descriptor 3.
At the end of the transfer, zero in this register indicates the
successful transfer, and a non-zero value indicates error
occurrence at the destination during descriptor 3 transfer.
Table 171 • HPDMAICR_REG
Bit
Number Name
Reset
Value Description
0 HPDMAICR_CLR_XFR_INT[0] 0 When this bit is set, HPDMA clears the following register bits:
Descriptor 0 Status register
HPDMASR_DCP_CMPLET[0]
HPDMASR_DCP_DERR[0]
HPDMASR_DCP_SERR[0]
HPDMA Empty Descriptor register
HPDMAEDR_DCP_NON_WORD_ERR[0]
1 HPDMAICR_CLR_XFR_INT[1] 0 When this bit is set, HPDMA clears the following register bits:
Descriptor 1 Status register
HPDMASR_DCP_CMPLET[1]
HPDMASR_DCP_DERR[1]
HPDMASR_DCP_SERR[1]
HPDMA Empty Descriptor register
HPDMAEDR_DCP_NON_WORD_ERR[1]
2 HPDMAICR_CLR_XFR_INT[2] 0 When this bit is set, HPDMA clears the following register bits:
Descriptor 2 Status register
HPDMASR_DCP_CMPLET[2]
HPDMASR_DCP_DERR[2]
HPDMASR_DCP_SERR[2]
HPDMA Empty Descriptor register
HPDMAEDR_DCP_NON_WORD_ERR[2]
3 HPDMAICR_CLR_XFR_INT[3] 0 When this bit is set, HPDMA clears the following register bits:
Descriptor 3 Status register
HPDMASR_DCP_CMPLET[3]
HPDMASR_DCP_DERR[3]
HPDMASR_DCP_SERR[3]
HPDMA Empty Descriptor register
HPDMAEDR_DCP_NON_WORD_ERR[3]
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