Microsemi SmartFusion2 - Cortex-M3 Processor Overview and Debug Features; Features

Cortex-M3 Processor Overview and Debug Features
UG0331 User Guide Revision 15.0 6
2 Cortex-M3 Processor Overview and Debug
Features
The ARM Cortex-M3 processor is a low power consumption processor that features low gate count, low
interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require
optimal interrupt response features. This processor implements the ARM v7-M architecture and is shown
in Figure 1, page 7. The SmartFusion
®
2 SoC FPGA device uses the R2P1 version of the Cortex-M3
core. This chapter highlights the Cortex-M3 processor and debug subsystem customizations made
specific to SmartFusion2.
For more details on the internals like programming model, exception model, instruction set, the
Cortex-M3 specific peripherals such as SysTick timer, memory protection unit and others, refer to the
Cortex-M3 Processor (Reference Material), page 18. The following manuals are available at the ARM
Info center:
• Cortex-M3 Technical Reference Manual
• ARM v7-M Architecture Reference Manual
• ARM v7-M Architecture Application Level Reference Manual
The Definitive Guide to the ARM Cortex-M3 by Joseph Yiu is recommended as additional reading (ISBN:
978-0-7506-8534-4).
2.1 Features
• A 32-bit processor core with low gate count and low latency interrupt processing.
• A RISC processor, with 3-stage pipeline Harvard architecture, pipeline core incorporating branch
speculation, single cycle multiplication, and hardware division, giving a Dhrystone benchmark of
1.25 DMIPS/MHz.
• A nested vectored interrupt controller (NVIC) that closely integrates with the processor core to
achieve low latency interrupt processing.
• A memory protection unit (MPU) is included. This facilitates the protected memory regions creation
and setting access rights for the protected regions.
• A Cortex-M3 processor, which is configured for SmartFusion2 MSS, and uses only little-endian.
• An auxiliary control register is included.
• Multiple high-performance bus interfaces that are connected through an advanced
high-performance bus (AHB).
• A debug solution with the optional ability to:
• Implement breakpoints and code patches
• Implement watchpoints, tracing, and system profiling
• Support print style debugging
• Bridge to a trace port analyzer
Manufacturers of Cortex-M3 processor integrated circuits are permitted some latitude in configuring a
particular implementation of the Cortex-M3 processor delivered by ARM. The following features are
implementation specifics in the SmartFusion2 device:
• MPU: This helps in creating protected and protected regions of memory
• Flash patch break point (FPB)
• Data watchpoint and trace (DWT) unit
• Instrumental trace macrocell (ITM)
• Embedded trace macrocell (ETM)
• Power-mode saving:
• HCLK is gated off when in SLEEPING or SLEEPDEEP mode.
SLEEPING and SLEEPDEEP signals are available at the FPGA fabric interface sleep mode exten-
sion handshake signals are available at the FPGA fabric interface.