Microsemi SmartFusion2 - Figure 5 Core Register Set; Table 7 Summary of Processor Mode, Execution Privilege Level, and Stack Use Options; Table 8 Core Register Set Summary

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 21
In Thread mode, the CONTROL register controls whether the processor uses the main stack or the
process stack, see CONTROL Register, page 27. In Handler mode, the processor always uses the main
stack. The options for processor operations are:
3.5.1.3 Core Registers
The following figure shows the processor core registers.
Figure 5 • Core Register Set
Table 7 • Summary of Processor Mode, Execution Privilege Level, and Stack Use Options
Processor mode Used to execute
Privilege level for
software execution Stack used
Thread Applications Privileged or
unprivileged
Main stack or process stack
Handler Exception handlers Always privileged Main stack
Table 8 • Core Register Set Summary
Name Type
1
Required
privilege
2
Reset value Description
R0-R12 RW Either Unknown General-Purpose Registers
MSP RW Privileged See description Stack Pointer
PSP RW Either Unknown Stack Pointer
LR RW Either 0xFFFFFFFF Link Register
PC RW Either See description Program Counter
PSR RW Privileged Unknown Program Status Register
ASPR RW Either Unknown Application Program Status Register
IPSR RO Privileged 0x00000000 Interrupt Program Status Register
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low Registers
High Registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose Registers
Stack Pointer
Link Register
Program Counter
Program Status Register
Exception Mask Registers
CONTROL Register
Special Registers
‡
Banked version of SP