Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 121
If calibration information is not known, calculate the calibration value required from the frequency of the
processor clock or external clock.
3.7.3.5 SysTick Design Hints and Tips
The SysTick counter runs on the processor clock. If this clock signal is stopped for Low-power mode, the
SysTick counter stops.
Ensure software uses aligned word accesses to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset, the correct initialization sequence
for the SysTick counter is:
1. Program reload value.
2. Clear current value.
3. Program Control and Status register.
3.7.4 Memory Protection Unit
This section describes the Memory protection unit (MPU).
The MPU divides the memory map into a number of regions, and defines the location, size, access
permissions, and memory attributes of each region. It supports:
• independent attribute settings for each region
• overlapping regions
• export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 processor
MPU defines:
• eight separate memory regions, 0-7
• a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 processor MPU memory map is unified. This means instruction accesses and data
accesses have same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
MemManage fault. This causes a fault exception, and might cause termination of the process in an OS
environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process
to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types, see Memory Regions, Types and Attributes,
page 29.
[29:24] Reserved.
[23:0] TENMS Reads as zero. Indicates calibration value is not known.
Table 75 • SYST_CALIB Register Bit Assignments (continued)
Bits Name Function
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