Microsemi SmartFusion2 - Table 185 Channel_X_Buffer_A_Transfer_Count

Peripheral DMA
UG0331 User Guide Revision 15.0 282
9.4.1.7 CHANNEL_x_BUFFER_A_TRANSFER_COUNT Register Bit Definition
9.4.1.8 CHANNEL_x_BUFFER_B_SRC_ADDR Register Bit Definition
9.4.1.9 CHANNEL_x_BUFFER_B_DST_ADDR Register Bit Definition
9.4.1.10 CHANNEL_x_BUFFER_B_TRANSFER_COUNT Register Bit Definition
Table 185 • CHANNEL_x_BUFFER_A_TRANSFER_COUNT
Bit Number Name
Reset
Value Description
[31:16] Reserved 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
[15:0] BUF_A_COUNT 0 Number of remaining transfers to be completed between source and
destination for buffer A for this channel. This field is decremented after
every DMA transfer cycle.
Writing a non-zero value to this register causes the DMA to start. This
must be the last register written by firmware when setting up a DMA
transfer.
Table 186 • CHANNEL_x_BUFFER_B_SRC_ADDR
Bit Number Name
Reset
Value Description
[31:0] BUF_B_SRC 0 Start address from which data is to be read during the next DMA
transfer cycle. If PERIPHERAL_DMA = 1 and DIR = 0, this value is not
incremented from one DMA transfer cycle to the next. Otherwise, it is
always incremented by an amount corresponding to the
TRANSFER_SIZE for this channel.
Table 187 • CHANNEL_x_BUFFER_B_DST_ADDR
Bit Number Name
Reset
Value Description
[31:0] BUF_B_DST 0 Start address from which data is to be write during the next DMA
transfer cycle. If PERIPHERAL_DMA = 1 and DIR = 1, this value is not
incremented from one DMA transfer cycle to the next. Otherwise, it is
always incremented by an amount corresponding to the
TRANSFER_SIZE for this channel.
Table 188 • CHANNEL_x_BUFFER_B_TRANSFER_COUNT
Bit Number Name
Reset
Value Description
[31:16] Reserved 0 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
[15:0] BUF_B_COUNT 0 Number of remaining transfers to be completed between source and
destination for buffer B for this channel. This field is decremented after
every DMA transfer cycle.
Writing a non-zero value to this register causes the DMA to start. This
must be the last register to be written by firmware when setting up a
DMA transfer.