System Register Block
UG0331 User Guide Revision 15.0 729
22.3.95 Fabric Protected Base Address Register
The value of N depends on the protected region size, so that the base address is aligned according to an
even multiple of region size. The power of 2 size specified by SW_PROTREGIONSIZE[4:0] defines how
many bits of base address are used. For example, if the SW_PROTREGIONSIZE[4:0] is 01111, this
corresponds to a protected region of 64 KB. 64 KB is 2 to the power of 16. Therefore the value of N in this
case is 16. So the base address of the region, in this case, is specified by SW_PROTREGIONBASE[31:16].
0 1 1 0 0 Reserved
01 1 0 1 16 KB
01 1 1 0 32 KB
01 1 1 1 64 KB
1 0 0 0 0 128 KB
1 0 0 0 1 256 KB
1 0 0 1 0 512 KB
1 0 0 1 1 Reserved
1 0 1 0 0 Reserved
1 0 1 0 1 Reserved
10 1 1 0 8 Mbytes
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
Table 753 • FAB_PROT_BASE
Bit
Number Name
Reset
Value Description
[31:0] SW_PROTREGIONBASE 0 The base address of the memory region inaccessible to the
FPGA fabric master is determined by the value of this bus. Bit 0
of this bus is defined as SW_PROTREGIONENABLE. This has
the following meaning:
0: Protected region not enabled. This means that a master in the
FPGA fabric may access any location in the memory map, as
long as the fabric master port is enabled.
1: Protected region enabled. Any accesses attempted by a
fabric master to this region of memory return an error in the bus
transaction.
Bits [31:N] of this bus indicate the base address of the protected
region.
Table 752 • Region Size (continued)
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Size
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