Microsemi SmartFusion2 - DDRB Status Register

System Register Block
UG0331 User Guide Revision 15.0 726
22.3.85 DDRB Status Register
22.3.86 MDDR IO Calibration Status Register
Table 742 • DDRB_STATUS
Bit
Number Name
Reset
Value Description
[31:0] DDRB_DEBUG_STATUS 0x1 Status of the internal ports of DDRBRIDGE. The bit definitions
are as follows:
Debug ports of the MSS DDR bridge:
SYR_DDRB_DP[31:30] = DSG write buffer mode status
SYR_DDRB_DP[29:28] = AHB bus write buffer mode status
SYR_DDRB_DP[27:26] = HPDMA write buffer mode status
SYR_DDRB_DP[25:23] = IDC read buffer mode status
SYR_DDRB_DP[22:20] = DSG read buffer mode status
SYR_DDRB_DP[19:17] = AHB bus read buffer mode status
SYR_DDRB_DP[16:14] = HPDMA read buffer mode status
SYR_DDRB_DP[13] = DSG write request to arbiter
SYR_DDRB_DP[12] = AHB bus write request to arbiter
SYR_DDRB_DP[11] = HPDMA write request to arbiter
SYR_DDRB_DP[10] = IDC read req to arbiter
SYR_DDRB_DP[9] = DSG read req to arbiter
SYR_DDRB_DP[8] = AHB bus read req to arbiter
SYR_DDRB_DP[7] = HPDMA read request to arbiter
SYR_DDRB_DP[6] = AXI write address channel acknowledge to
DSG write request
SYR_DDRB_DP[5] = AXI write address channel acknowledge to
AHB bus write request
SYR_DDRB_DP[4] = AXI write address channel acknowledge to
HPDMA write request
SYR_DDRB_DP[3] = AXI write data channel acknowledge to
DSG write request
SYR_DDRB_DP[2] = AXI write data channel acknowledge to
AHB bus write request
SYR_DDRB_DP[1] = AXI write data channel acknowledge to
HPDMA write request
SYR_DDRB_DP[0] = Lock input to arbiter from AHB bus WCB
Table 743 • MDDR_IO_CALIB_STATUS
Bit
Number Name
Reset
Value Description
[31:15] Reserved 0
14 CALIB_PCOMP 0x1 State of the P analog comparator
13 CALIB_NCOMP 0x1 State of the N analog comparator
[12:6] CALIB_PCODE 0x3F Current PCODE value set on the MDDR DDR I/O bank
[5:1] CALIB_NCODE 0x3F Current NCODE value set on the MDDR DDR I/O bank
0 CALIB_STATUS 0 1 when the codes are actually locked. For the first run after
reset, this would be asserted 1 cycle after CALIB_INTRPT. For
in-between runs, this would be asserted only when the DRAM
is put into self-refresh or there is an override from the firmware
(CALIB_LOCK).