Microsemi SmartFusion2 - Receive Message Control and Command Register

CAN Controller
UG0331 User Guide Revision 15.0 460
12.6.7 Receive Message Control and Command Register
Each receive buffer can be configured through a set of registers. Those registers are broken down into a
Command/Control register, Identifier register, Data high register, and Data low register, Acceptance mask
register (AMR), Acceptance code register (ACR), AMR data, and ACR data. The following tables provide
a detailed description of receive message0 buffer registers bits.
Table 450 • RX_MSG0_CTRL_CMD
Bit Number Name Reset Value Description
[31:24] Reserved 0 Reserved
23 WPNH 1 Write protect not high
0: Bit[21:16] remain unchanged
1: The write protect is not set and bit[21:16] are modified,
default
The read back value of this bit is undefined
22 Reserved 0 Reserved
21 RTR 0 RTR bit; Control bit
0: This is a regular message
1: This is an RTR message.
20 IDE 0 Extended identifier bit; Control bit
0: This is a standard format message.
1: This is an extended format message.
[19:16] DLC 0 Data length code; Control bits
0: Message has 0 data byte.
1: Message has 1 data byte.
...
8: Message has 8 data bytes.
9-15: Message has 8 data bytes.
[15:8] Reserved 0 Reserved
7 WPNL 1 Write protect not low
0: Bits[6:3] remain unchanged
1: This write protect is not set and bits[6:3] are modified,
default.
This bit is always zero for read back
6 LF 0 Link flag; Control bit
0: This buffer is not linked to the next
buffer
1: This buffer is linked with the next buffer
5 RxIntEbl 0 Receive interrupt enable; Control bit
0: Interrupt generation is disabled
1: Interrupt generation is enabled
4 RTRreply 0 Automatic message reply upon receipt of an RTR
message; Control bit
0: Automatic RTR message handling disabled
1: Automatic RTR message handling enabled
3 TxBufferEbl 0 Transaction buffer enable; Control bit
0: Buffer is disabled
1: Buffer is enabled