Microsemi SmartFusion2 - Table 641 WDOGCONTROL; Table 642 WDOGSTATUS; Table 643 WDOGRIS

Watchdog Timer
UG0331 User Guide Revision 15.0 640
Table 641 • WDOGCONTROL
Bit Number Name Reset Value Description
[31:3] Reserved 0 To provide compatibility to the future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
2 MODE WDOGMODE Operation mode for the watchdog timer.
0: reset is generated if counter reaches zero.
1: interrupt is generated if counter reaches zero.
This read only register holds the value of user flash bit written in
the WDOGMODE bit of the WDOG_CR system register.
1 WAKEUPINTEN 0 0: The WDOGWAKEUPINT interrupt generation is disabled.
1: The WDOGWAKEUPINT interrupt generation is enabled.
0 TIMEOUTINTEN 0 0: The WDOGTIMEOUTINT interrupt generation is disabled.
1: The WDOGTIMEOUTINT interrupt generation is enabled.
Table 642 • WDOGSTATUS
Bit Number Name Reset Value Description
[31:1] Reserved 0 To provide the compatibility to the future products, the value of a
reserved bit should be preserved across a read-modify-write
operation
0 REFRESHSTATU
S
0 Refresh status
0: The counter is in forbidden window, refresh should not be
initiated.
1: The counter in is permitted window, refresh is allowed.
Table 643 • WDOGRIS
Bit Number Name Reset Value Description
[31:2] Reserved 0 To provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
1 WAKEUPRS 0 Raw status of wakeup interrupt.
Writing '1' to this bit clears the bit. Writing '0' has no effect.
0 TIMEOUTRS 0 Raw status of counter timeout interrupts.
Writing '1' to this bit clears the bit. Writing '0' has no effect.