System Register Block
UG0331 User Guide Revision 15.0 681
USERCONFIG1 0x178 RO-P SYSRESET_
N
User Configuration Register 1
USERCONFIG2 0x17C RO-P SYSRESET_
N
User Configuration Register 2
USERCONFIG3 0x180 RO-P SYSRESET_
N
User Configuration Register 3
FAB_PROT_SIZE 0x184 RO-P SYSRESET_
N
Size of memory protected from
fabric master
FAB_PROT_BASE 0x188 RO-P SYSRESET_
N
Base address which is protected
from fabric master
MSS_GPIO_DEF 0x18C RO-P SYSRESET_
N
MSS GPIO Definition Register
EDAC_SR 0x190 SW1C SYSRESET_
N
Status of 1-bit SECDED error
detection and correction, 2-bit
SECDED error detection for
eSRAM0, eSRAM1, MAC, USB,
and CAN
MSS_INTERNAL_SR 0x194 SW1C SYSRESET_
N
MSS Internal Status Register
MSS_EXTERNAL_SR 0x198 SW1C SYSRESET_
N
MSS External Status Register
WDOGTIMEOUTEVENT 0x19C SW1C PORESET_N Watchdog Time out event
register
CLR_MSS_COUNTERS 0x1A0 W1P SYSRESET_
N
Clear MSS counters
CLR_EDAC_COUNTERS 0x1A4 W1P SYSRESET_
N
Clears 16-bit counter value in
eSRAM0, eSRAM1, MAC, USB,
and CAN corresponding to
count value of EDAC 1-bit and
2-bit errors
FLUSH_CR 0x1A8 W1P SYSRESET_
N
Flush Control Register
MAC_STAT_CLR_CR 0x1AC W1P SYSRESET_
N
MAC Statistics Clear Control
Register
IOMUXCELL_CONFIG[n]
n is 0 to 56
0x1B0 to
0x290
RW-P Register PORESET_N I/O MUXCELL Configuration
Register
Table 650 • SYSREG (continued)
Register Name
Addr.
Offset
Register
Type
Flash
Write
Protect Reset Source Description