Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 336
10.3.8.8 RX_FIFO_ADD_REG Bit Definitions
10.3.8.9 VBUS_CSR_REG (write only control) Bit Definitions
10.3.8.10 VBUS_CSR_REG (read only status) Bit Definitions
10.3.8.11 HW_VERSION_REG Bit Definitions
Table 248 • RX_FIFO_ADD_REG (0x40043066)
Bit
Number Name
Reset
Value Function
13 Reserved N/A
[12:0] AD[12:0] 0 Start address of the receive endpoint FIFO in units of 8 bytes as given in
Table 247, page 336.
Table 249 • VBUS_CSR_REG (write only) (0x40043068)
Bit
Number Name
Reset
Value Function
[3:0] Vcontrol 0 Vendor-specific control data
Table 250 • VBUS_CSR_REG (read only) (0x40043068)
Bit
Number Name
Reset
Value Function
[7:0] Vstatus 0 Vendor-specific status data
Table 251 • HW_VERSION_REG (0x4004306C)
Bit
Number Name
Reset
Value Function
15 Reserved N/A
[14:10] xx 0 Major version number (range 0–31)
[9:0] yyy 0 Minor version number (range 0–999)