Microsemi SmartFusion2 - Revision 3.0; Revision 2.0; Revision 1.0; Table 59 Table

Revision History
UG0331 User Guide Revision 15.0 4
• Updated Table 611, page 612 (SAR 42472).
• Updated Power-On Reset, page 654 (SAR 45905).
• Updated Table 650, page 676, Ta b le 69 3, page 704, and Ta bl e 71 5, page 714 (SAR 48598).
• Updated details for CC_EDAC_EN in Ta bl e 66 9, page 691 (SAR 48194).
• Updated Table 735, page 722 (SAR 44275 and 48634).
• Updated Table 763, page 736 (SAR 49501).
• Updated details for CC_EDAC_EN in Ta bl e 13 8, page 208 (SAR 48194)
1.13 Revision 3.0
The following changes were made in revision 3.0 of this document.
• Updated "Purpose" section (SAR 48036).
• Updated Table 321, page 378 (SAR 47908).
• Updated links in CAN Controller, page 436 (SAR 47608).
• Restructured Fabric Interface Controller, page 757 as per inputs (SAR 47958).
1.14 Revision 2.0
The following changes were made in revision 2.0 of this document.
• Modified the title of the user guide (SAR 45509).
• Restructured Cortex-M3 Processor Overview and Debug Features, page 6 (SAR 44811).
• Restructured Cache Controller, page 133 (SAR 44811).
• Restructured Embedded NVM (eNVM) Controllers, page 145 and updated AHBL Address Map to
NVM, page 150 (SAR 40367).
• Restructured Embedded SRAM (eSRAM) Controllers, page 187 (SAR 45900).
• Restructured AHB Bus Matrix, page 210 (SAR 46456).
• Restructured High Performance DMA Controller, page 236 (SAR 46151).
• Restructured Peripheral DMA, page 264 (SAR 46422).
• Restructured Universal Serial Bus OTG Controller, page 284 (SAR 47042).
• Restructured Ethernet MAC, page 374 (SAR 47043).
• Restructured CAN Controller, page 436 (SAR 50262).
• Restructured MMUART Peripherals, page 469 (SAR 50262).
• Restructured Serial Peripheral Interface Controller, page 504 (SAR 50262).
• Restructured Inter-Integrated Circuit Peripherals, page 538 (SAR 50262).
• Restructured MSS GPIO, page 562 (SAR 50262).
• Restructured Communication Block, page 592 (SAR 50262).
• Restructured RTC System, page 601 (SAR 46060).
• Restructured System Timer, page 614 (SAR 46048).
• Restructured Watchdog Timer, page 629 (SAR 46053).
• Restructured Reset Controller, page 642 and updated Power-Up to Functional Time Sequence,
page 645 (SAR 42469).
• Updated Figure 294, page 660 (SAR 43874).
• Restructured System Register Block, page 670 (SAR 47001).
• Updated the "Flash Write ProtectSYSREG Block Register Write Protection" section (SAR 41978).
• Updated Ta bl e 6 5 7, page 686, Table 739, page 724, Table 764, page 737, and Ta ble 76 5, page 737
(SARs 43008 and 42733).
• Restructured Fabric Interface Interrupt Controller, page 738 (SAR 50262).
• Restructured Fabric Interface Controller, page 757 (SAR 45631).
• Restructured APB Configuration Interface, page 784 (SAR 50262).
• Updated DDR Remap, page 229 (SAR 42910).
• Updated
Table 779, page 760 (SAR 45578).
1.15 Revision 1.0
Revision 1.0 was the first publication of this document.
• Updated Cache Controller, page 133 (SAR 41865).
• Table 89, page 135, Figure 57, page 134, and Table 91, page 137 (SAR 41865).
• Added Figure 250, page 593 (SAR 41229).