Microsemi SmartFusion2 - Table 728 MM0_1_2_SECURITY; Table 729 MM4_5_DDR_FIC_SECURITY;MM4_5_FIC64_SECURITY; Security Configuration Register for Masters 0, 1, and 2

System Register Block
UG0331 User Guide Revision 15.0 718
22.3.71 Security Configuration Register for Masters 0, 1, and 2
22.3.72 Security Configuration Register for Masters 4, 5, and DDR_FIC
Table 728 • MM0_1_2_SECURITY
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0
9 MM0_1_2_MS6_ALLOWED_W 1 Write security bits for masters 0, 1, and 2 to slave 6 (MSS
DDR bridge). If not set, masters 0, 1, and 2 will not have write
access to slave 6.
8 MM0_1_2_MS6_ALLOWED_R 1 Read security bits for masters 0, 1, and 2 to slave 6 (MSS
DDR bridge). If not set, masters 0, 1, and 2 will not have read
access to slave 6.
7 MM0_1_2_MS3_ALLOWED_W 1 Write security bits for masters 0, 1, and 2 to slave 3 (eNVM1).
If not set, masters 0, 1, and 2 will not have write access to
slave 3.
6 MM0_1_2_MS3_ALLOWED_R 1 Read security bits for masters 0, 1 and 2 to slave 3 (eNVM1).
If not set, masters 0, 1, and 2 will not have read access to
slave 3.
5 MM0_1_2_MS2_ALLOWED_W 1 Write security bits for masters 0, 1, and 2 to slave 2 (eNVM0])
If not set, masters 0, 1, and 2 will not have write access to
slave 2.
4 MM0_1_2_MS2_ALLOWED_R 1 Read security bits for masters 0, 1, and 2 to slave 2 (eNVM0).
If not set, masters 0, 1, and 2 will not have read access to
slave 2.
3 MM0_1_2_MS1_ALLOWED_W 1 Write security bits for masters 0, 1, and 2 to slave 1
(eSRAM1). If not set, masters 0, 1, and 2 will not have write
access to slave 1.
2 MM0_1_2_MS1_ALLOWED_R 1 Read security bits for masters 0, 1, and 2 to slave 1
(eSRAM1). If not set, masters 0, 1, and 2 will not have read
access to slave 1.
1 MM0_1_2_MS0_ALLOWED_W 1 Write security bits for masters 0, 1, and 2 to slave 0
(eSRAM0). If not set, masters 0, 1, and 2 will not have write
access to slave 0.
0 MM0_1_2_MS0_ALLOWED_R 1 Read security bits for masters 0, 1, and 2 to slave 0
(eSRAM0). If not set, masters 0, 1, and 2 will not have read
access to slave 0.
Table 729 • MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0
9 MM4_5_DDR_FIC_MS6_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to
slave 6 (MSS DDR bridge). If not set, masters 4, 5 and
DDR_FIC will not have write access to slave 6.
8 MM4_5_DDR_FIC_MS6_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to
slave 6 (MSS DDR bridge). If not set, masters 4, 5, and
DDR_FIC will not have read access to slave 6.