Microsemi SmartFusion2 - Figure 40 SHCSR Bit Assignments; Table 63 SHCSR Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 111
3.7.2.9 System Handler Control and State Register
The SHCSR enables the system handlers, and indicates:
• the pending status of the BusFault, MemManage fault, and SVC exceptions
• the active status of the system handlers.
See the register summary in Ta ble 50 , page 102 for the SHCSR attributes. The bit assignments are:
Figure 40 • SHCSR Bit Assignments
Table 63 • SHCSR Bit Assignments
Bits Name Function
[31:19] - Reserved
[18] USGFAULTENA UsageFault enable bit, set to 1 to enable
1
[17] BUSFAULTENA BusFault enable bit, set to 1 to enable
a
[16] MEMFAULTENA MemManage enable bit, set to 1 to enable
a
[15] SVCALLPENDED SVCall pending bit, reads as 1 if exception is pending
2
[14] BUSFAULTPENDED BusFault exception pending bit, reads as 1 if exception is pending
b
[13] MEMFAULTPENDED MemManage fault exception pending bit, reads as 1 if exception is pending
b
[12] USGFAULTPENDED UsageFault exception pending bit, reads as 1 if exception is pending
b
[11] SYSTICKACT SysTick exception active bit, reads as 1 if exception is active
3
[10] PENDSVACT PendSV exception active bit, reads as 1 if exception is active
[9] - Reserved
[8] MONITORACT Debug monitor active bit, reads as 1 if Debug monitor is active
[7] SVCALLACT SVCall active bit, reads as 1 if SVC call is active
[6:4] - Reserved
[3] USGFAULTACT UsageFault exception active bit, reads as 1 if exception is active
[2] - Reserved
[1] BUSFAULTACT BusFault exception active bit, reads as 1 if exception is active
USGFAULTENA
SVCALLPENDED
BUSFAULTENA
MEMFAULTENA
BUSFAULTPENDED
SYSTICKACT
PENDSVACT
MONITORACT
SVCALLACT
USGFAULTACT
BUSFAULTACT
MEMFAULTACT
MEMFAULTPENDED
USGFAULTPENDED
Reserved
Reserved
Reserved
Reserved
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0