Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 24
3.5.1.3.8 Execution Program Status Register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction.
See the register summary in Ta ble 8, page 21 for the EPSR attributes. The following table lists the bit
assignments.
Attempts to read the EPSR directly using the MRS instruction always return zero. Attempts to write the
EPSR using the MSR instruction are ignored.
[8:0] ISR_NUMBER This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = HardFault
4 = MemManage
5 = BusFault
6 = UsageFault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0.
.
.
.
255 = IRQ239
See Exception Types, page 37 for more information
Table 12 • EPSR Bit Assignments
Bits Name Function
[31:27] Reserved.
[26:25], [15:10] ICI/IT Indicates the interrupted position of a continuable
instruction, or the execution state of an IT instruction (see
IT, page 85).
[24] T Thumb state bit.
[23:16] Reserved.
[9:0] Reserved.
Table 11 • IPSR Bit Assignments
Bits Name Function
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