Microsemi SmartFusion2 - Features; Figure 204 Microcontroller Subsystem Showing SPI Peripherals

Serial Peripheral Interface Controller
UG0331 User Guide Revision 15.0 504
14 Serial Peripheral Interface Controller
Serial peripheral interface (SPI) is a synchronous serial data protocol that enables the microprocessor or
microcontroller and peripheral devices to communicate with each other. The SPI controller is an APB
slave in the SmartFusion2 device that provides a serial interface compliant with the Motorola SPI, Texas
Instruments synchronous serial, and National Semiconductor MICROWIRE™ formats. In addition, SPI
supports interfacing with large SPI flash and EEPROM devices and a hardware-based slave protocol
engine.
14.1 Features
SmartFusion2 SPI peripherals support the following features:
• Master and Slave modes
• Selectable slaves up to 8
• Configurable slave select operation
• Configurable clock polarity
• Separate transmit (Tx) and receive (Rx) FIFOs to reduce interrupt service loading
• Processor controlled and PDMA controlled mode of data transfer
The following figure shows details of the microcontroller subsystem (MSS). The SPI peripherals are
interfaced to the AHB bus matrix through the APB interfaces (APB_0 and APB_1).
Figure 204 • Microcontroller Subsystem Showing SPI Peripherals
AHB Bus Matrix
eSRAM_0
System
Controller
Cache
Controller
SD IC
ARM Cortex-M3
Processor
SDI
MSS DDR
Bridge
PDMA
MS6
MM3
AHB To AHB Bridge with Address Decoder
USB OTG
HPDMA
MDDR
APB_0
SYSREG
Triple Speed
Ethernet MAC
FIC_0
MM4 MS4
MS2 MS3 MS0
MS5
MS1
MM5 MM6
MM7
MM8
MM2 MM1 MM0 MM9
IDC
D/S
eNVM_0 eNVM_1 eSRAM_1
FIC_2 (Peripheral
Initialization)
APB_1
MMUART_0
SPI_0
I2C_0
PDMA
Configuration
WATCHDOG
FIIC
TIMERx2
MMUART_1
SPI_1
I2C_1
GPIO
CAN
RTC
COMM_BLK
FIC_1
MSS_FIC MS6_USB
MS5_MAC MS5_SR MS5_APB0 MS5_FIC2 MS5_APB1