Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 316
COUNT0_REG 0x40043018 7 R 0 Indicates the number of received data bytes in the
endpoint 0 FIFO. The value returned changes as
the contents of the FIFO change and is only valid
while RxPktRdy (CSR0L_REG.bit0) is set.
RX_COUNT_REG 0x40043018 14 R 0 Holds the number of data bytes in the packet
currently in line to be read from the Rx FIFO. If the
packet is transmitted as multiple bulk packets, the
number given will be for the combined packet.
The value returned changes as the FIFO is
unloaded and is only valid while RxPktRdy
(CSR0L_REG.bit0) is set.
TYPE0_REG 0x4004301A 8 RW 0 Applicable in Host mode only. Number of received
bytes in endpoint0 FIFO (Index register set to
select endpoint 0).
TX_TYPE_REG 0x4004301A 8 RW 0 Number of bytes to be read from the peripheral
receive endpoint FIFO (Index register set to select
endpoints 1 – 4).
NAK_LIMIT0_REG 0x4004301B 5 RW 0 Sets the NAK response timeout on endpoint 0
(Index register set to select endpoint 0).
TX_INTERVAL_REG 0x4004301B 8 RW 0 Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on bulk
transactions for host transmit endpoint (Index
register set to select endpoints 1 – 4 only).
RX_TYPE_REG 0x4004301C 8 RW 0 Sets the transaction protocol, speed, and
peripheral endpoint number for the host receive
endpoint (Index register set to select endpoints 1 –
4 only).
RX_INTERVAL_REG 0x4004301D 8 RW 0 Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on bulk
transactions for host receive endpoint (Index
register set to select endpoints 1 – 4 only).
CONFIG_DATA_REG 0x4004301F 8 R Returns details of USB controller configuration
(Index register set to select endpoint 0).
FIFO_SIZE_REG 0x4004301F 8 R Returns the configured size of the selected
receive and transmit FIFOs (endpoints 1 – 4 only).
Table 211 • Indexed Register Set Description (continued)
Register Name Address Width
R/W
Type
Reset
Value Description
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