Microsemi SmartFusion2 - Figure 68 Read Path; Table 96 AHBL Address Map to NVM

Embedded NVM (eNVM) Controllers
UG0331 User Guide Revision 15.0 150
The following figure shows the eNVM array read path.
The AHB Controller also supports WRAP4 burst operations, which are initiated by the cache controller. In
this case, the AHB eNVM controller will automatically perform four 64-bit read operations (critical word
first) and fill the read data buffer in advance to the AHB read transactions to increase system throughput.
Figure 68 • Read Path
In the eNVM array, the addresses are 64-bit locations; therefore each page of 1,024 bits (16 double
words = 32 words) requires an AHBL address map, as specified in the following table.
When programming the eNVM, sector and page addresses must be programmed into the command
(CMD) register, as specified in Ta bl e 98 , page 151.
5.2.4.3 eNVM Commands
The eNVM commands are explained in the Table 98, page 151. The eNVM Command register is used to
program the eNVM commands. The following section explains the details of the eNVM Command
register.
Table 96 • AHBL Address Map to NVM
Sector Number Page Number in Sector Address in Page Byte Number in 64-Bit Data
HADDR[17:12] HADDR[11:7] HADDR[6:3] HADDR[2:0]
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