Microsemi SmartFusion2 - Figure 37 SHPR1 Bit Assignments; Figure 38 SHPR2 Bit Assignments; Figure 39 SHPR3 Bit Assignments

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 110
3.7.2.8.1 System Handler Priority Register 1
The bit assignments are:
Figure 37 • SHPR1 Bit Assignments
3.7.2.8.2 System Handler Priority Register 2
The bit assignments are:
Figure 38 • SHPR2 Bit Assignments
3.7.2.8.3 System Handler Priority Register 3
The bit assignments are:
Figure 39 • SHPR3 Bit Assignments
Table 60 • SHPR1 Bit Assignments
Bits Name Function
[31:24] PRI_7 Reserved
[23:16] PRI_6 Priority of system handler 6, UsageFault
[15:8] PRI_5 Priority of system handler 5, BusFault
[7:0] PRI_4 Priority of system handler 4, MemManage
Table 61 • SHPR2 Bit Assignments
Bits Name Function
[31:24] PRI_11 Priority of system handler 11, SVCall
[23:0] Reserved
Table 62 • SHPR3 Bit Assignments
Bits Name Function
[31:24] PRI_15 Priority of system handler 15, SysTick exception
[23:16] PRI_14 Priority of system handler 14, PendSV
[15:0] Reserved
31 24 23 0
Reserved PRI_6 PRI_5 PRI_4
16 15 8 7
31 24 23 0
PRI_11 Reserved
PRI_15
31 15 01624 23
PRI_14 Reserved