Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 199
MM9_SECURITY
(0x40038130)
RO-U N/A SYSRESET_N Read and Write security for Mirrored
Master (MM) 9 to eSRAM_0 and
eSRAM_1. This register gets updated
by flash bit configuration set during
device programming. This configuration
can be done through the System
Builder using settings on the Security
tab.
EDAC_SR
(0x40038190)
SW1C N/A SYSRESET_N Status of 1-bit ECC error detection and
correction (EDAC), 2-bit ECC error
detection for eSRAM_0 and eSRAM_1.
Individual register bits are set (1) when
related input is asserted. Bits are
individually cleared when corresponding
register bit is written High.
CLR_EDAC_COUNTERS
(0x400381A4)
W1P N/A SYSRESET_N This is used to clear the 16-bit counter
value in eSRAM_0 and eSRAM_1
corresponding to the count value of
EDAC 1-bit and 2-bit errors.
EDAC_IRQ_ENABLE_CR
(0x40038078)
RW-P Register SYSRESET_N Enable/disable of 1-bit error, 2-bit error
status update for eSRAM_0 and
eSRAM_1. This can be set by the
System Builder also using settings on
the SECDED tab.
EDAC_CR
(0x40038038)
RW-P Register SYSRESET_N EDAC enable/disable and soft reset for
eSRAM_0 and eSRAM_1. This can be
set by the System Builder also using
settings on the SECDED tab.
Table 123 • ESRAM_CR
Bit
Number Name
Reset
Value Description
[31:2] Reserved 0 Reserved
1 SW_CC_ESRAM1FWREMAP 0 Defines the locations of eSRAM_0 and eSRAM_1 if eSRAM
remap is enabled (if SW_CC_ESRAMFWREMAP is asserted). If
SW_CC_ESRAMFWREMAP is 0, this bit has no meaning. If
SW_CC_ESRAMFWREMAP is 1, this bit has the following
definition:
0: eSRAM_0 is located at address 0x00000000 in the
ICODE/DCODE space of Cortex-M3 processor and eSRAM_1 is
located just above eSRAM_0 (adjacent to it).
1: eSRAM_1 is located at address 0x00000000 in
ICODE/DCODE space of Cortex-M3 processor and eSRAM_0 is
located just above eSRAM_1 (adjacent to it).
Table 122 • SYSREG Control Registers (continued)
Register Name
Register
Type
Flash Write
Protect Reset Source Description
To Next Page
Loading...
