Communication Block
UG0331 User Guide Revision 15.0 595
This mechanism allows the receiver to verify that no bytes have been lost and stops it from accidentally
interpreting data overruns as command. The RCVOKAY and TXTOKAY status bits must be checked in
the STATUS register before reading and writing data or command.
17.2.3 Clocks
APB Interface, Control and Status block, and SII Interface are clocked by PCLK1 from the APB1 bus. RX
FIFO and TX FIFO are clocked by data clock (50 MHz RC oscillator). PCLK is derived from the fabric
aligned clock controller (FACC) output. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking
Resources User Guide.
17.2.4 Resets
The COMM_BLK resets to zero on power-up and is held in reset until it is enabled. There is an option to
reset the COMM_BLK by writing to the system register.
Specifically, this system register is SOFT_RESET_CR in the System Register Block, page 670. The
COMBLK_SOFTRESET control bit is encoded in bit location 15 as follows:
0: COMM_BLK reset released
1: COMM_BLK held in reset (reset value)
At power-up, the reset signal is asserted 1. This keeps the COMM_BLK peripheral in a reset state. If this
bit is set to 0, the COMM_BLK peripheral is allowed to become active.
17.2.5 Interrupts
There is one interrupt signal from the COMM_BLK peripheral. The COMBLK_INTR/COMMS_INT signal
is mapped to INTISR[19] in the Cortex-M3 processor nested vectored interrupt controller (NVIC) and also
goes to the FPGA fabric through the FIIC. The interrupt in the COMM_BLK peripheral must be enabled
by setting the appropriate bits in the interrupt enable register. Clear the appropriate bit in the Interrupt
Enable Register when servicing the COMMS_INT to prevent a reassertion of the interrupt.
17.2.6 COMM_BLK Initialization
The COMM_BLK peripheral can be initialized by configuring the COMM_BLK Control Register and
SOFT_RESET_CR system register. The initialization sequence is as follows:
1. Release the COMM_BLK from reset by using SOFT_RESET_CR system registry (refer to the
Resets, page 595 for further details)
2. Enable COMM_BLK by writing 1 to the ENABLE bit of Control Register.
3. Disable the loopback by writing '0' to the LOOPBACK bit in the Control Register.
17.2.7 CoreSysServices Soft IP
COMM_BLK is used to call the following system services:
• Device and Design Information Services
• Flash*Freeze Service
• Cryptographic Services
• DPA-Resistant Key-Tree Services
• Non-Deterministic Random Bit Generator (NRBG) Services
• Zeroization Service
• Programming Service
• NVM Data Integrity Check Service
Microsemi provides CoreSysServices soft IP to access the system services implemented by the System
Controller from FPGA fabric. The CoreSysServices soft IP provides a user interface for each of the
system services and an advanced high-performance bus (AHB)-Lite master interface on the fabric
interface controller (FIC) side. The core communicates with the COMM_BLK through one of the fabric
interface controllers (FICs).
The CoreSysServices soft IP decodes the command received from the user logic and translates the user
logic transactions to the AHB-Lite master transactions. For more information on CoreSysServices soft IP,
refer to the CoreSysServices Handbook available in the Libero SoC IP catalog.
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