Microsemi SmartFusion2 - SYSREG Control Registers; Table 122 SYSREG Control Registers; Esram_Max_Lat; Esram_Pipeline_Cr

Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 198
6.4 SYSREG Control Registers
The registers listed in the following table control the behavior of the eSRAM. These registers are detailed
in SYSREG and are listed here for clarity. Refer to the System Register Block, page 670 for a detailed
description of each register and bit.
Table 122 • SYSREG Control Registers
Register Name
Register
Type
Flash Write
Protect Reset Source Description
ESRAM_CR (0x40038000) RW-P Register SYSRESET_N Controls address mapping of the
eSRAMs.
ESRAM_MAX_LAT
(0x40038004)
RW-P Register SYSRESET_N Configuration of maximum latency for
accessing eSRAM_0 and eSRAM_1
slaves. This register gets updated by
flash bit configuration set during device
programming. This configuration can be
done through the System Builder also
using settings on the Microcontroller
Tab.
ESRAM_PIPELINE_CR
(0x40038080)
RW-P Register SYSRESET_N Controls the pipeline present in the
memory read path of eSRAM memory.
ESRAM0_EDAC_CNT
(0x400380F0)
RO N/A SYSRESET_N Represents 1-bit error count of
eSRAM_0.
ESRAM1_EDAC_CNT
(0x400380F4)
RO N/A SYSRESET_N Represents 1-bit error count of
eSRAM_1.
ESRAM0_EDAC_ADR
(0x4003810C)
RO N/A SYSRESET_N Address from eSRAM_0 on which 1-bit
ECC error has occurred.
ESRAM1_EDAC_ADR
(0x40038110)
RO N/A SYSRESET_N Address from eSRAM_1 on which 1-bit
ECC error has occurred.
MM0_1_2_SECURITY
(0x40038124)
RO-U N/A SYSRESET_N Read and Write security for Mirrored
Master (MM) 0, 1, and 2 to eSRAM_0
and eSRAM_1.
MM4_5_DDR_FIC_SECUR
ITY/MM4_5_FIC64_SECU
RITY(0x40038128)
RO-U N/A SYSRESET_N Read and Write security for Mirrored
Master (MM) 4, 5, and DDR_FIC to
eSRAM_0 and eSRAM_1. This register
gets updated by flash bit configuration
set during device programming. This
configuration can be done through the
System Builder using settings on the
Security tab.
MM3_6_7_8_SECURITY
(0x4003812C)
RO-U N/A SYSRESET_N Read and Write security for Mirrored
Master (MM) 3, 6, 7, and 8 to eSRAM_0
and eSRAM_1. This register gets
updated by flash bit configuration set
during device programming. This
configuration can be done through the
System Builder using settings on the
Security tab.