Reset Controller
UG0331 User Guide Revision 15.0 646
The power up to functional sequence is as follows:
• Supply Ramp (VDD, VPP, VDDI, and VDDAPLL) - There is no specific power up or power down
sequencing requirement for SmartFusion2 devices. The I/O banks can be brought-up in any order,
before or after the core voltage. However, the device is only functional if all I/O bank supplies are
powered-up.
• On power-up, the POR generator block asserts the PO_RESET_N signal, which is not accessible for
users.
• The 1 MHz RC Oscillator is turned-on, which provides the clock to the programmable delay counter.
When the counter reaches its maximum value, the PO_RESET_N signal is de-asserted.
• The 1 MHz RC oscillator is gated off and the 50 MHz RC oscillator is enabled and the System
Controller starts operating at 50 MHz clock.
• All mandatory I/O bank supplies must be powered-up. For all the IGLOO
®
2 devices, some of the
bank supplies (VDDIx) must always be powered, even if associated bank I/Os are in unused
condition. For the list of mandatory I/O bank supplies, refer to Table 2 and Table 3 in the AC393:
SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.
• FPGA fabric (LSRAM, uSRAM, and MATH), FDDR, and SERDES are turned-on.
• Input buffer is enabled.
• POWER_ON_RESET_N signal (generated from the PO_RESET_N signal) is released. This signal
can be used in the design as a reset for the FPGA fabric logic.
• Fabric PLL (Fabric CCC) Lock is asserted.
• MSS reset (SC_MSS_RESET_N) is released.
• MPLL (MSS CCC) Lock is asserted.
• MSS to Fabric Reset (MSS_RESET_N_M2F) is released.
• Output buffer is enabled.
The Reset Controller Configurator in the MSS Configurator enables the user to expose the
MSS_RESET_N_M2F signal to the fabric. Refer to How to Use the Reset Controller, page 666 for more
information. In order to simplify the task of initializing a user design in SmartFusion2 devices, Microsemi
provides a CoreResetP soft Reset Controller IP. The CoreResetP handles sequencing of reset signals in
SmartFusion2 devices. The CoreResetP generates a fabric reset signal whenever
POWER_ON_RESET_N is asserted or MSS_RESET_N_M2F is asserted. It is available in the Libero
SoC IP catalog. Refer to CoreResetP Soft Reset Controller, page 660 for more information.
Note: Microsemi recommends using the System Builder which automatically creates the 'initialization' sub-
system (all required cores are Instantiated, and connections are made automatically).
21.2 Power-Up to Functional Time Data
This section describes power-up to functional time sequence and provides timing numbers based on
DEVRST_N assertion and VDD ramp up.
21.2.1 Parameters Used for Obtaining Power-Up to Functional Time
Data
This section describes the parameters used for obtaining power-up to functional time data. Following are
the test conditions:
• Power on reset delay setting: 1 ms
• Supply ramp rate: 5 µs
• Measurement temperature: 25°C
Power-on reset delay setting indicates how long VDD takes to ramp up. The programmable delay
counter starts counting based on the power-on reset delay setting, oscillator frequency, and period
variability to ensure that the supplies have reached their minimum operating levels.
Supply ramp rate indicates the ramp up rate of on-board VDD core voltage, VPP charge pump voltage,
and VDDA phase-locked loop (PLL) analog voltage supplies.
Note: In all the test cases, I/Os are configured as LVCMOS25, which is the default I/O standard in Libero along
with the other default I/O attribute settings.
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