Microsemi SmartFusion2 - Figure 279 Power up to Functional Time Sequence Diagram

Reset Controller
UG0331 User Guide Revision 15.0 645
configuration. For more details on DEVRST_N timing information, refer to the DS0451: IGLOO2 and
SmartFusion2 Datasheet.
Asserting DEVRST_N does not enable the delay counter (Power on Reset Delay) in the POR circuitry.
The delay counter is operational only at power-up. When DEVRST_N is low, all user I/Os are fully tri-
stated. Although, the JTAG I/Os are still enabled, they cannot be used as the TAP controller is in reset.
The SYSRESET macro is not required to be instantiated to enable the DEVRST_N pin in the user
design. DEVRST_N is a dedicated input-only reset pad available on all the SmartFusion2 devices.
21.1.2 Power-Up to Functional Time Sequence
The following figure shows the power up to functional time sequence diagram.
Figure 279 • Power up to Functional Time Sequence Diagram
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