Microsemi SmartFusion2 - MSS DDR Bridge Buffer Timer Control Register

System Register Block
UG0331 User Guide Revision 15.0 689
22.3.12 MSS DDR Bridge Buffer Timer Control Register
22.3.13 MSS DDR Bridge Non-Bufferable Address Control Register
22.3.14 MSS DDR Bridge Non-Bufferable Size Control Register
The following table lists the size of the non-bufferable region, given by the formula [(2N – 1x64)] KB.
Table 664 • DDRB_BUF_TIMER_CR
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0
[9:0] DDRB_TIMER 0x3FF 10-bit timer interface used to configure the timeout register in the
write buffer module. Once timer reaches the timeout value, a flush
request is generated by the flush controller and if response has
been received for previous write request from write arbiter, this
request is posted to the write arbiter. This register is common for all
buffers. The value in this register will be in terms of number of
M3_CLK clocks.
Table 665 • DDRB_NB_ADDR_CR
Bit
Number Name
Reset
Value Description
[31:16] Reserved 0
[15:0] DDRB_NB_ADDR 0xA000 Base address of a non-bufferable address region.
Bits [15:(N – 1)] of this signal are compared with AHB address
[31:(N + 15)] to check whether address is in non-bufferable region.
The value of N depends on the non-bufferable region size, so the
base address is defined according to DDRB_NB_SZ.
Table 666 • DDRB_NB_SIZE_CR
Bit
Number Name
Reset
Value Description
[31:16
4] Reserved 0
[3:0] DDRB_NB_SZ 0x1 Size of non-bufferable address region [(2N – 1x64) KB]. The region
sizes are as shown in Table 667, page 689.
Table 667 • Non-Bufferable Region
Bit 0 Bit 1 Bit 2 Bit 3 N Non-Bufferable Region
0 0 0 0 0 No non-bufferable region
0 0 0 1 1 64 KB = (21 – 1 x 64) KB
0 0 1 0 2 128 KB = (22 – 1 x 64) KB
0 0 1 1 3 256 KB = (23 – 1 x 64) KB
0 1 0 0 4 512 KB = (24 – 1 x 64) KB
0 1 0 1 5 1 MB = (25 – 1 x 64) KB