Microsemi SmartFusion2 - HPDMA Register Bit Definitions

High Performance DMA Controller
UG0331 User Guide Revision 15.0 247
8.4.1 HPDMA Register Bit Definitions
8.4.1.1 HPDMA Empty Descriptor Register
Table 150 • HPDMAEDR_REG
Bit
Number Name
Reset
Value Description
0 HPDMAEDR_DCP_EMPTY[0] 1 Descriptor 0 is empty and ready for software
configuration.
1: Descriptor 0 is empty and ready to configure.
0: Descriptor 0 is already configured and descriptor
transfer is in progress/queue.
At the end of the descriptor transfer, either on transfer
error or transfer done, the HPDMA controller asserts
this bit High.
1 HPDMAEDR_DCP_EMPTY[1] 1 Descriptor 1 is empty and ready for software
configuration.
1: Descriptor 1 is empty and ready to configure.
0: Descriptor 1 is already configured and descriptor
transfer is in progress/queue.
At the end of the descriptor transfer, either on transfer
error or transfer done, the HPDMA controller asserts
this bit High.
2 HPDMAEDR_DCP_EMPTY[2] 1 Descriptor 2 is empty and ready for software
configuration.
1: Descriptor 2 is empty and ready to configure.
0: Descriptor 2 is already configured and descriptor
transfer is in progress/queue.
At the end of the descriptor transfer, either on transfer
error or transfer done, the HPDMA controller asserts
this bit High.
3 HPDMAEDR_DCP_EMPTY[3] 1 Descriptor 3 is empty and ready for software
configuration.
1: Descriptor 3 is empty and ready to configure.
0: Descriptor 3 is already configured and descriptor
transfer is in progress/queue.
At the end of the descriptor transfer, either on transfer
error or transfer done, the HPDMA controller asserts
this bit High.
4 HPDMAEDR_DCP_CMPLET[0] 0 Descriptor 0 transfer complete.
1: Descriptor 0 transfer completed successfully.
0: Descriptor 0 transfer not completed.
When the descriptor 0 transfer is completed, either
with transfer error or transfer done, HPDMA controller
asserts this bit High.
This bit is cleared on writing ‘1’ to the
HPDMAICR_CLR_XFR_INT[0] bit of the HPDMA
Interrupt Clear register or when the
HPDMACR_DCP_VALID[0] bit of descriptor 0 Control
register is set.