Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 38
For an asynchronous exception, other than reset, the processor can execute another instruction between
when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 22, page 39 shows as having configurable
priority. See
System Handler Control and State Register, page 112 and Interrupt Clear-enable Registers, page 97.
For more information about HardFaults, MemManage faults, BusFaults, and UsageFaults, see Fault
Handling, page 43.
3.5.3.3 Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs): Interrupts IRQ0 to IRQ239 are the exceptions handled by ISRs.
Fault handlers: HardFault, MemManage, UsageFault and BusFault are fault exceptions handled by the
fault handlers.
System handlers: NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions
that are handled by system handlers.
Table 22 • Properties of the Different Exception Types
Exception
number
1
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than
interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register, page 23.
IRQ number
1
Exception type Priority
Vector address or
offset
2
2. See Vector Table, page 40 for more information.
Activation
1 Reset -3, the highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 HardFault -1 0x0000000C
4 -12 MemManage Configurable 0x00000010 Synchronous
5 -11 BusFault Configurable
3
3. See System Handler Priority Registers, page 110.
0x00000014 Synchronous when precise,
asynchronous when
imprecise
6 -10 UsageFault Configurable
3
0x00000018 Synchronous
7-10 Reserved
11 -5 SVCall Configurable
3
0x0000002C Synchronous
12-13 Reserved
14 -2 PendSV Configurable
3
0x00000038 Asynchronous
15 -1 SysTick Configurable
3
0x0000003C Asynchronous
16 and
above
0 and above Interrupt (IRQ) Configurable
4
4. See Interrupt Priority Registers, page 99.
0x00000040 and
above
5
5. Increasing in steps of 4.
Asynchronous
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