MSS GPIO
UG0331 User Guide Revision 15.0 578
16.4.6 GPIO System Reset Control Register
16.4.7 I/O MUX Associated With GPIOs
The following table shows the associated IOMUXes for GPIOs.
The following tables (Table 546, page 579 through Table 591 on page 591) describe the IOMUXes in
which GPIOs are shared with the peripheral and the fabric.
Table 544 • GPIO_SYSRESET_SEL_CR
Bit
Number Name
Reset
Value Description
[31:4] Reserved 0 Reserved
3 MSS_GPIO_31_24_SYSRESET_SEL 0 0: The GPIO[31:24] is reset by either power-on reset or
the MSS_GPIO_RESET_N signal from the FPGA fabric.
1: The GPIO[31:24] is reset by the soft reset signal
MSS_GPIO_31_24_SOFT_RESET.
2 MSS_GPIO_23_16_SYSRESET_SEL 0 0: The GPIO[23:16] is reset by either power-on reset or
the MSS_GPIO_RESET_N signal from the FPGA fabric.
1: The GPIO[23:16] is reset by the soft reset signal
MSS_GPIO_23_16_SOFT_RESET.
1 MSS_GPIO_15_8_SYSRESET_SEL 0 0: The GPIO[15:8] is reset by either power-on reset or
the MSS_GPIO_RESET_N signal from the FPGA fabric.
1: The GPIO[15:8] is reset by the soft reset signal
MSS_GPIO_15_8_SOFT_RESET.
0 MSS_GPIO_7_0_SYSRESET_SEL 0 0: The GPIO[7:0] is reset by either power-on reset or the
MSS_GPIO_RESET_N signal from the FPGA fabric.
1: The GPIO[7:0] is reset by the soft reset signal
MSS_GPIO_7_0_SOFT_RESET.
Table 545 • Associated IOMUXes for GPIOs
Peripheral Associated IOMUXes
GPIOA[0] to GPIOA[10] 11 to 21
GPIOA[11] to GPIOA[18] 26 to 33
GPIOA[19] to GPIOA[22] 22 to 25
GPIOA[23] to GPIOA[24] 34 to 35
GPIOB[11] to GPIOB[16] 36 to 41
GPIOB[17] to GPIOB[22] 45 to 50
GPIOB[23] 56
GPIOB[24] to GPIOB[26] 42 to 44
GPIOB[27] to GPIOB[31] 51 to 55
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