MMUART Peripherals
UG0331 User Guide Revision 15.0 499
13.4.12 Modem Status Register (MSR)
3 FE R 0 Framing error (FE). Indicates that the receive byte did not have a valid
stop bit. FE is cleared when Cortex-M3 processor reads the LSR. The
MMUART_x tries to resynchronize after a framing error. To do this, it
assumes that the framing error was due to the next start bit, so it samples
this start bit twice, and then starts receiving the data. This error is revealed
to Cortex-M3 processor when it is associated character is at the top of the
FIFO.
2 PE R 0 Parity error (PE). Indicates that the receive byte had a parity error. PE is
cleared when the Cortex-M3 processor reads the LSR. This error is
revealed to the Cortex-M3 processor when it is associated character is at
the top of the FIFO.
1 OE R 0 Overrun error (OE). Indicates that the new byte was received before the
Cortex-M3 processor reads the byte from the receive buffer, and that the
earlier data byte was destroyed. OE is cleared when the Cortex-M3
processor reads the LSR. If the data continues to fill the FIFO beyond the
trigger level, an overrun error occurs once the FIFO is full and the next
character has been completely received in the shift register. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
0 DR R 0 Data ready (DR). Indicates when a data byte is received and stored in the
receive buffer or the FIFO. DR is cleared to 0 when the Cortex-M3
processor reads the data from the receive buffer or the FIFO.
Table 483 • MSR
Bit
Number Name R/W
Reset
Value Description
7 DCD R 0 Data carrier detect (DCD) (MMUART_x_DCD).The complement of DCD
input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to
OUT2 in the MCR.
6 RI R 0 Ring indicator (RI) (MMUART_x_RI). The complement of the RI input.
When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to OUT1 in
the MCR.
5 DSR R 0 Data set ready (DSR) (MMUART_x_DSR). The complement of the DSR
input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to RTS
in the MCR.
4 CTS R 0 Clear to send (CTS) (MMUART_x_CTS). The complement of the CTS
input. When bit 4 of the MCR is set to 1 (loop), this bit is equivalent to DTR
in the MCR
.
3 DDCD R 0 Delta data carrier detect (DDCD) indicator. Indicates that DCD input has
changed state.
Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is
generated.
2 TERI R 0 Trailing edge of ring indicator (TERI) detector. Indicates that RI input has
changed from 0 to 1.
Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is
generated.
Table 482 • LSR (continued)
Bit
Number Name R/W
Reset
Value Description
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