Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 124
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in "Memory Model" on page 25.
Any access by privileged software that does not address an enabled memory region behaves as
defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory region causes a
MemManage fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the
ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are
enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory
attributes as if the MPU is not implemented, see Table 17, page 30. The default memory map applies to
accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted.
Other areas are accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a HardFault or NMI
exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when
operating with these two priorities.
3.7.4.3 MPU Region Number Register
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR
registers. See the register summary in Table 77, page 123 for its attributes. The bit assignments are:
Figure 52 • SYST_CVR Register Bit Assignments
[2] PRIVDEFENA Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables use of the default memory map. Any memory
access to a location not covered by any enabled region causes a fault.
1: If the MPU is enabled, enables use of the default memory map as a background
region for privileged software accesses.
When enabled, the background region acts as if it is region number -1. Any region that
is defined and enabled has priority over this default map.
If the MPU is disabled, the processor ignores this bit.
[1] HFNMIENA Enables the operation of MPU during HardFault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during HardFault, NMI, and FAULTMASK handlers, regardless of
the value of the ENABLE bit
1: the MPU is enabled during HardFault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
[0] ENABLE Enables the MPU:
0: MPU disabled
1: MPU enabled
Table 79 • MPU_CTRL Register Bit Assignments (continued)
Bits Name Function
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