Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0 200
The following table gives eSRAM maximum latency values, where x is either 0 or 1.
0 SW_CC_ESRAMFWREMAP 0 This bit indicates that eSRAM_0 and eSRAM_1 are remapped to
lCODE/DCODE space of the Cortex-M3 processor. If this bit is 1
and SW_CC_ESRAM1FWREMAP is 0, then eSRAM_0 is at
location 0x00000000 and eSRAM_1 is always remapped to be
just above eSRAM_0 (the two eSRAMs are adjacent in
ICODE/DCODE space). Both eSRAMs also remain visible in
SYSTEM space of the Cortex-M3 processor and remain visible at
this location to all other (non-Cortex-M3 processor) masters. The
bit definitions:
0: No eSRAM remap is enabled. This means that eNVM (or
MDDR) is present at location 0x00000000.
1: eSRAM_0 and eSRAM_1 are remapped to location
0x00000000 of Cortex-M3 processor ICODE/DCODE space.
Table 124 • ESRAM_MAX_LAT
Bit
Number Name
Reset
Value Description
[31:6] Reserved 0 Reserved
[5:3] SW_MAX_LAT_ESRAM1 0x1 Defines the maximum number of cycles the processor bus will
wait for eSRAM1 when it is being accessed by a master with a
weighted round robin (WRR) priority scheme. The latency values
are as given in Table 125, page 200.
[2:0] SW_MAX_LAT_ESRAM0 0x1 Defines the maximum number of cycles the processor bus will
wait for eSRAM0 when it is being accessed by a master with a
WRR priority scheme. It is configurable from 1 to 8 (8 by default).
The latency values are as given in Table 125, page 200.
Table 125 • eSRAM Maximum Latency Values
SW_MAX_LAT_ESRAM<X> Latency
0 8 (default)
11
22
33
44
55
66
77
Table 123 • ESRAM_CR (continued)
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