Microsemi SmartFusion2 - Table 274 Endpoint3 Control and Status Registers

Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 345
10.3.10.4 Endpoint3 Control and Status Registers
EP2_RX_CSR_REG 0x0126 16 R 0 Provides control and status bits for transfers
through the receive endpoint2.
EP2_RX_COUNT_REG 0x0128 16 R 0 Holds the number of data bytes in the packet
currently in line to be read from the endpoint2
receive FIFO. If the packet is transmitted as
multiple bulk packets, the number given will be
for the combined packet.
EP2_TX_TYPE_REG 0x012A 8 W 0 Reads the number of bytes from peripheral
endpoint2 transmit FIFO.
EP2_TX_INTERVAL_REG 0x012B 8 RW 0 Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host transmit endpoint2.
EP2_RX_TYPE_REG 0x012C 8 RW 0 Sets the transaction protocol, speed, and
peripheral endpoint number for the host receive
endpoint2.
EP2_RX_INTERVAL_REG 0x012D 8 RW 0 Sets the polling interval for interrupt/ISOC
transactions or the NAK response timeout on
bulk transactions for host receive endpoint2.
EP2_FIFO_SIZE_REG 0x012E 8 R Returns the configured size of the endpoint2
receive FIFO and transmit FIFOs.
Table 274 • Endpoint3 Control and Status Registers
Register Name
Address
Offset from
0x40043000 Width
R/W
Type
Reset
Value Description
EP3_TX_MAX_P_REG 0x0130 16 RW 0 Maximum packet size for host transmit
endpoint3.
EP3_TX_CSR_REG 0x0132 16 R 0 Provides control and status bits for transmit
endpoint3.
EP3_RX_MAX_P_REG 0x0134 16 RW 0 Defines the maximum amount of data that can be
transferred through receive endpoint3 in a single
operation.
EP3_RX_CSR_REG 0x0136 16 R 0 Provides control and status bits for transfers
through the receive endpoint3.
EP3_RX_COUNT_REG 0x0138 16 R 0 Holds the number of data bytes in the packet
currently in line to be read from the endpoint3
receive FIFO. If the packet is transmitted as
multiple bulk packets, the number given will be
for the combined packet.
EP3_TX_TYPE_REG 0x013A 8 W 0 Reads the number of bytes from peripheral
endpoint3 transmit FIFO.
Table 273 • Endpoint2 Control and Status Registers (continued)
Register Name
Address
Offset from
0x40043000 Width
R/W
Type
Reset
Value Description