Microsemi SmartFusion2 - Saturating Instructions

Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0 78
3.6.6.2.3 Restrictions
In these instructions:
• do not use SP and do not use PC
•
RdHi and RdLo must be different registers.
3.6.6.2.4 Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
3.6.6.3 SDIV and UDIV
Signed Divide and Unsigned Divide.
3.6.6.3.1 Syntax
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see Conditional Execution, page 55.
Rd is the destination register. If
Rd is omitted, the destination register is Rn .
Rn is the register holding the value to be divided.
Rm is a register holding the divisor.
3.6.6.3.2 Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm .
UDIV performs an unsigned integer division of the value in Rn by the value in Rm .
For both instructions, if the value in
Rn is not divisible by the value in Rm , the result is rounded towards
zero.
3.6.6.3.3 Restrictions
Do not use SP and do not use PC .
3.6.6.3.4 Condition Flags
These instructions do not change the flags.
Examples
SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1.
3.6.7 Saturating Instructions
This section describes the saturating instructions, SSAT and USAT .
3.6.7.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.