System Register Block
UG0331 User Guide Revision 15.0 736
22.3.105 IOMUXCELL_CONFIG[n] Configuration Register
Notes:
• Bit 0, Bit 1, and Bit 2 in the following table refer to IOMUXSEL5LOWER, IOMUXCELL5MID,
IOMUXCELL5UPPER respectively.
• Do not change these register fields dynamically for 005 and 010 devices, see "System Registers
Behavior for M2S005/010 Devices" section on page 682.
Table 763 • IOMUXCELL_CONFIG[n]
Bit
Number Name
Reset
Value Description
[31:10] Reserved 0
9 MSS_IOMUXSEL5LOWER[N] 0 Used to select the source of the output port of the I/O cell
corresponding to this IOMUXCELL. Each bit of this bus is
used together with the corresponding bit of
MSS_IOMUXSEL5UPPER and MSS_IOMUXSEL5MID to
form a 3-bit field. This field definition is in Table 764, page 737.
8 MSS_IOMUXSEL5MID[N] 0 Used to select the source of the output port of the I/O cell
corresponding to this IOMUXCELL
7 MSS_IOMUXSEL5UPPER[N] 0 Used to select the source of the OE port of the I/O cell
corresponding to this IOMUXCELL
6:4 MSS_IOMUXSEL4[N][2:0] 0 Used to select the source of the output port of the I/O cell
corresponding to this IOMUXCELL. This field definition is in
Table 765 on page 737.
3 MSS_IOMUXSEL3[N] 0 0: Output enable of interface MSS GPIO of IOMUXCELL goes
to FPGA fabric core input
1: Output of interface serial comms of IOMUXCELL goes to
FPGA fabric core input
2 MSS_IOMUXSEL2[N] 0 0: Output of interface MSS GPIO of IOMUXCELL goes to
FPGA fabric core input
1: Output enable of interface serial comms of IOMUXCELL
goes to FPGA fabric core input
1 MSS_IOMUXSEL1[N] 0 0: Input of interface MSS GPIO of IOMUXCELL comes from
the output of interface FPGA fabric core
1: Input of interface MSS GPIO of IOMUXCELL comes from
the I/O cell input
0 MSS_IOMUXSEL0[N] 0 0: Input of interface serial comms of IOMUXCELL comes from
the output of interface FPGA fabric core
1: Input of interface serial comms of IOMUXCELL comes from
the I/O cell input
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