Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0 355
10.3.12.2 DMA_INT_REG Bit Definitions
10.3.12.3 CHx_DMA_CTRL_REG Bit Definitions
CH4_DMA_CTRL_REG 0x0234 10 RW 0 This register provides the DMA transfer control for
Channel 4. The enabling, transfer direction, Transfer
mode, and the DMA burst modes are controlled by
this register.
CH4_DMA_ADDR_REG 0x0238 32 RW 0 Identifies the current memory address of DMA
channel 4. The initial memory address written to this
register must have a value such that its modulo 4
value is equal to 0. That is,
CH4_DMA_ADDR_ADDR[1:0] must be equal to 00.
The lower two bits of this register are only read and
cannot be set by the software. As the DMA transfer
progresses, the memory address is incremented as
bytes are transferred.
CH4_DMA_COUNT_REG 0x023C 32 RW 0 Identifies the current DMA count of the transfer for
DMA channel 4. Software sets the initial count of the
transfer, which identifies the entire transfer length. As
the count progresses, this count is decremented as
bytes are transferred.
Table 293 • DMA_INT_REG (0x40043200)
Bit
Number Name Reset Value Function
[7:4] Reserved N/A
3 CH4_DMA_INTR 0 Channel4 DMA interrupt
2 CH3_DMA_INTR 0 Channel3 DMA interrupt
1 CH2_DMA_INTR 0 Channel2 DMA interrupt
0 CH1_DMA_INTR 0 Channel1 DMA interrupt
[7:4] Reserved N/A
Table 294 • CHx_DMA_CTRL_REG (0x40043204)
Bit
Number Name
Reset
Value Function
[10:9] DMA_BRSTM 0 Burst Mode
00: Burst mode 0; bursts of unspecified length
01: Burst mode 1; INCR4 or unspecified length
10: Burst mode 2; INCR8, INCR4 or unspecified length
11: Burst mode 3; INCR16, INCR8, INCR4, or unspecified length
Table 292 • DMA_REGISTER Description (continued)
Register Name
Address
Offset
from
0x400430
00 Width
R/W
Type
Reset
Value Description
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