Microsemi SmartFusion2 - High Performance DMA Controller; Figure 120 HPDMA Interfacing with MSSDDR Bridge and AHB Bus Matrix

High Performance DMA Controller
UG0331 User Guide Revision 15.0 236
8 High Performance DMA Controller
The high performance DMA Controller (HPDMA) provides fast data transfer between the MSS DDR
bridge and MSS memories. The MSS memories are eSRAM0, eSRAM1, eNVM0, and eNVM1. The DDR
bridge connects to External DDR memory.
The following figure shows HPDMA interfacing with AHB Bus Matrix and MSS DDR bridge. AHB bus
masters such as the Cortex-M3 processor can offload the high speed memory transfers to HPDMA,
making the master available for performing other tasks. All transfers by the HPDMA are full word
transfers. The HPDMA controller has two AHB masters, MSS DDR Bridge and AHB bus matrix master
(MM0-MM9) which functions concurrently to enable high performance data transfers. The configuration
of HPDMA is done through the APB interface.
One of the main applications for which the HPDMA can be used is paging access by the processor. The
main data is stored in a large DDR space and relevant chunks of this data would be transferred as
needed via the HPDMA to the eSRAM, where it can be processed faster.
Figure 120 • HPDMA Interfacing With MSSDDR Bridge and AHB Bus Matrix
AHB Bus Matrix
eSRAM_0
System
Controller
Cache
Controller
SD IC
ARM Cortex-M3
Processor
SDI
MSS DDR
Bridge
PDMA
MS6
MM3
AHB To AHB Bridge with Address Decoder
USB OTG
HPDMA
MDDR
APB_0
SYSREG
Triple Speed
Ethernet MAC
FIC_0
MM4 MS4
MS2 MS3 MS0
MS5
MS1
MM5 MM6
MM7
MM8
MM2 MM1 MM0 MM9
IDC
D/S
eNVM_0 eNVM_1 eSRAM_1
FIC_2 (Peripheral
Initialization)
APB_1
MMUART_0
SPI_0
I2C_0
PDMA
Configuration
HPDMA
Configuration
WATCHDOG
FIIC
TIMERx2
MMUART_1
SPI_1
I2C_1
GPIO
CAN
RTC
COMM_BLK
FIC_1
MSS_FIC MS6_USB
MS5_MAC MS5_SR MS5_APB0 MS5_FIC2 MS5_APB1