Revision History
UG0331 User Guide Revision 15.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 15.0
The following changes were made in revision 15.0 of this document.
• Configuration Through Libero Software and Firmware, page 16 updated.
• TESMAC Firmware Drivers information updated in Table 327, page 391, Table 328, page 391,
Table 329, page 391, Tab le 33 0, page 392.
• Updated register information in Ta b le 46 8, page 491, Table 666, page 689, Table 693, page 704,
Table 722, page 716, Tab l e 72 3, page 716, Table 724, page 717, Table 725, page 717, Ta b le 72 6,
page 717, and Table 727, page 717.
• Updated ULPI (UTMI+ Low Pin Interface) I/O Interface, page 287.
1.2 Revision 14.0
The following changes were made in revision 14.0 of this document.
• The power-up to functional time sequence information was updated to include the
POWER_ON_RESET_N signal. For more information, see Power-Up to Functional Time Sequence,
page 645.
• The test cases listed in Table 645, page 648 were updated for consistency with DS0128: IGLOO2
and SmartFusion2 Datasheet. The VDD power-up to functional time flow diagram (Figure 282,
page 650) was updated to include the POWER_ON_RESET_N signal. For more information, see
VDD Power-Up to Functional Time, page 648.
• The test cases listed in Table 646, page 651 were updated for consistency with DS0128: IGLOO2
and SmartFusion2 Datasheet. The DEVRST_N power-up to functional time flow diagram
(Figure 283, page 651) was updated to include the POWER_ON_RESET_N signal. For more
information, see DEVRST_N Power-Up to Functional Time, page 651.
1.3 Revision 13.0
The following changes were made in revision 13.0 of this document.
• Updated Power Management, page 45 (SAR 84698).
• Updated Table 72, page 120 (SAR 83563).
• Added System Registers Behavior for M2S005/010 Devices, page 682 (SAR 83541).
• Updated Table 738, page 724 (SAR 83014).
• Updated Software Reset Control Register, page 693 (SAR 82129).
• Updated Figure 82, page 160, Figure 83, page 160, Figure 84, page 161, Figure 85, page 161, and
Figure 86, page 162 (SAR 85251).
• Updated Table 113, page 184 (SAR 85241).
1.4 Revision 12.0
The following changes were made in revision 12.0 of this document.
• Updated Table 650, page 676 (SAR 70453).
• Updated bit name from MSS_IOMUXSEL4UPPER[N] to MSS_IOMUXSEL4[N][2:0] in the Table 763,
page 736 (SAR 78918).
• Added Register Lock Bits Configuration, page 674 (SAR 79854).
• Updated Table 777, page 758 (SAR 78910).
• Updated Power-On Reset Generation Sequence, page 643 (SAR 76102).
• Updated Bit number [18:1] description in Table 658, page 686 (SAR 69988).
• Updated Register name CLRHINT[2:0] row in Table 112, page 180 (SAR 74635).
• Updated £ to in Cortex-M3 Processor Overview and Debug Features, page 6 (SAR 76277).
• Added Figure 85, page 161 (M2S060 device) (SAR 78896).
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