System Register Block
UG0331 User Guide Revision 15.0 714
22.3.57 MSS DDR Bridge Buffer Empty Status Register
22.3.58 MSS DDR Bridge Disable Buffer Status Register
Table 714 • DDRB_BUF_EMPTY_SR
Bit
Number Name
Reset
Value Description
[31:7] Reserved 0
6 DDRB_IDC_RBEMPTY 0 When set to ‘1’, indicates that the read buffer of the IDC master
does not have valid data.
5 DDRB_HPD_RBEMPTY 0 When set to ‘1’, indicates that the read buffer of the HPDMA
master does not have valid data.
4 DDRB_HPD_WBEMPTY 0 When set to ‘1’, indicates that the write buffer of the HPDMA
master does not have valid data.
3 DDRB_SW_RBEMPTY 0 When set to ‘1’, indicates that the read buffer of the AHB bus
matrix master does not have valid data.
2 DDRB_SW_WBEMPTY 0 When set to ‘1’, indicates that the write buffer of the AHB bus
matrix master does not have valid data.
1 DDRB_DS_RBEMPTY 0 When set to ‘1’, indicates that the read buffer of the DSG
master does not have valid data.
0 DDRB_DS_WBEMPTY 0 When set to ‘1’, indicates that the write buffer of the DSG
master does not have valid data.
Table 715 • DDRB_DSBL_DN_SR
Bit
Number Name
Reset
Value Description
[31:7] Reserved 0
6 DDRB_IDC_DSBL_DN 0 Is set to ‘1’ once the AHB bus matrix read buffer is disabled
after getting a read buffer disable command from processor.
5 DDRB_HPD_RDSBL_DN 0 Is set to ‘1’ once the HPDMA read buffer is disabled after
getting a read buffer disable command from processor.
4 DDRB_HPD_WDSBL_DN 0 Is set to ‘1’ once the HPDMA write buffer is disabled after
getting a write buffer disable command from processor.
3 DDRB_SW_RDSBL_DN 0 Is set to ‘1’ once the AHB bus matrix read buffer is disabled
after getting a read buffer disable command from processor.
2 DDRB_SW_WDSBL_DN 0 Is set to ‘1’ once the AHB bus matrix write buffer is disabled
after getting a write buffer disable command from processor.
1 DDRB_DS_RDSBL_DN 0 Is set to ‘1’ once the DS read buffer is disabled after getting a
read buffer disable command from processor.
0 DDRB_DS_WDSBL_DN 0 Is set to ‘1’ once the DS write buffer is disabled after getting a
write buffer disable command from processor.
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